Intel Corporation

Lori R Borger

Jason Sandri

Tina C Zhong

Kenneth P Griesser

Chee Hak Teh

Lance E Hacking

Ramana V Rachakonda

Mahesh K Reddy

John P Lee

Pawitter P Bhatia

In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Interface logic for a multi-core system-on-a-chip (SoC)

In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

On-die logic analyzer for semiconductor die

Growing community of inventors

Phoenix, AZ, United States of America

Lori R Borger