Cree Gmbh

Cree Research Inc.

Lori A Lipkin

John Williams Palmour

Mrinal Kanti Das

Scott Thomas Sheppard

Helmut Hagleitner

John Williams Paimour

Sei-Hyung Ryu

Anant Kumar Agarwal

David Beardsley Slater, Jr

Ranbir Singh

Alexander A Suvorov

Silicon carbide structures are fabricated by fabricating a nitrided oxide layer on a layer of silicon carbide and annealing the nitrided oxide layer in an environment containing hydrogen. Such a fabrication of the nitrided oxide layer may be provided by forming the oxide layer in at least one of nitric oxide and nitrous oxide and/or annealing an oxide layer in at least one of nitric oxide and nitrous oxide. Alternatively, the nitrided oxide layer may be provided by fabricating an oxide layer and fabricating a nitride layer on the oxide layer so as to provide the nitrided oxide layer on which the nitride layer is fabricated. Furthermore, annealing the oxide layer may be provided as a separate step and/or substantially concurrently with another step such as fabricating the nitride layer or performing a contact anneal. The hydrogen environment may be pure hydrogen, hydrogen combined with other gases and/or result from a hydrogen precursor. Anneal temperatures of 400&#xb0; C. or greater are preferred.

Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment

Capacitors and interconnection structures for silicon carbide are provided having an oxide layer, a layer of dielectric material and a second oxide layer on the layer of dielectric material. The thickness of the oxide layers may be from about 0.5 to about 33 percent of the thickness of the oxide layers and the layer of dielectric material. Capacitors and interconnection structures for silicon carbide having silicon oxynitride layer as a dielectric structure are also provided. Such a dielectric structure may be between metal layers to provide a metal-insulator-metal capacitor or may be used as a inter-metal dielectric of an interconnect structure so as to provide devices and structures having improved mean time to failure. Methods of fabricating such capacitors and structures are also provided.

Methods of fabricating high voltage, high temperature capacitor and interconnection structures

High voltage, high temperature capacitor and interconnection structures

Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) and methods of fabricating silicon carbide MOSFETs are provided. The silicon carbide MOSFETs have an n-type silicon carbide drift layer, spaced apart p-type silicon carbide regions in the n-type silicon carbide drift layer and having n-type silicon carbide regions therein, and a nitrided oxide layer. The MOSFETs also have n-type shorting channels extending from respective ones of the n-type silicon carbide regions through the p-type silicon carbide regions to the n-type silicon carbide drift layer. In further embodiments, silicon carbide MOSFETs and methods of fabricating silicon carbide MOSFETs are provided that include a region that is configured to self-deplete the source region, between the n-type silicon carbide regions and the drift layer, adjacent the oxide layer, upon application of a zero gate bias.

SILICON CARBIDE POWER METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING A SHORTING CHANNEL AND METHODS OF FABRICATING SILICON CARBIDE METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING A SHORTING CHANNEL

Methods for fabricating a layer of oxide on a silicon carbide layer are provided by forming the oxide layer on the silicon carbide layer by oxidizing the silicon carbide layer in an N O environment. A predetermined temperature profile and/or a predetermined flow rate profile of N O are provided during the oxidation. The predetermined temperature profile and/or predetermined flow rate profile may be constant or variable and may include ramps to steady state conditions. The predetermined temperature profile and/or the predetermined flow rate profile are selected so as to reduce interface states of the oxide/silicon carbide interface with energies near the conduction band of SiC.

Method of N2O growth of an oxide layer on a silicon carbide layer

Methods for fabricating a layer of oxide on a silicon carbide layer are provided by forming the oxide layer on the silicon carbide layer and then annealing the oxide layer in an N O environment at a predetermined temperature profile and at a predetermined flow rate profile of N O. The predetermined temperature profile and the predetermined flow rate profile are selected so as to reduce interface states of the oxide/silicon carbide interface with energies near the conduction band of SiC.

Method of N2O annealing an oxide layer on a silicon carbide layer

A dielectric structure is disclosed for silicon carbide-based semiconductor devices. In gated devices, the structure includes a layer of silicon carbide, a layer of silicon dioxide on the silicon carbide layer, a layer of another insulating material on the silicon dioxide layer, with the insulating material having a dielectric constant higher than the dielectric constant of silicon dioxide, and a gate contact to the insulating material. In other devices the dielectric structure forms an enhanced passivation layer or field insulator.

Layered dielectric on silicon carbide semiconductor structures

A monollithic CMOS integrated device formed in silicon carbide and method of fabricating same. The CMOS integrated device includes a layer of silicon carbide of a first conductivity type with a well region of a second conductivity type formed in the layer of silicon carbide. A MOS field effect transistor is formed in the well region and a complementary MOS field effect transistor is formed in the silicon carbide layer. The method of fabrication of CMOS silicon carbide includes formation of an opposite conductivity well region in a silicon carbide layer by ion implantation. Source and drain contacts are also formed by selective ion implantation in the silicon carbide layer and the well region. A gate dielectric layer is formed by deposition and reoxidation. A gate electrode is formed on the gate dielectric such that a channel region is formed between the source and the drain when a bias is applied to the gate electrode. Source drain and body contacts are preferably formed of the same material in a single fabrication step.

Silicon carbide CMOS devices

A method is disclosed for obtaining improved oxide layers and resulting improved performance from oxide based devices. The method comprises exposing an oxide layer on a silicon carbide layer to an oxidizing source gas at a temperature below the temperature at which SiC would begin to oxidize at a significant rate, while high enough to enable the oxidizing source gas to diffuse into the oxide layer, and while avoiding any substantial additional oxidation of the silicon carbide, and for a time sufficient to densify the oxide layer and improve the interface between the oxide layer and the silicon carbide layer.

Growing community of inventors

Raleigh, NC, United States of America

Lori A Lipkin