Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Lorenzo Papillo

Giona Fucili

Alberto Gola

Annamaria Rossi

Andrea Pasquino

Ezio Galbiati

Francesco Chrappan Soldavini

Alberto Salina

Agostino Mirabelli

Andrea Merello

Gianluca Ventura

Roberto Peritore

Francesco Vavala

Many integrated circuit die are fabricated on a wafer. Each die includes integrated functional circuitry with an array of fuse elements that are visible to optical inspection. An electrical wafer sort is performed to test the integrated functional circuitry of each die. The array of fuse elements for each die on the wafer are programmed through the electrical wafer sort process with data bits defining a die identification that specifies a location of the die on the wafer. The die is then encapsulated in a package. In the event of package failure, a decapsulation is performed to access the die. Optical inspection of the array of fuse elements is then made to extract the die identification.

Die identification by optically reading selectively blowable fuse elements

A method is provided for driving a load in a pulse width modulation (PWM) mode as a function of numeric command values having a predetermined number of N-bits. The method includes the step of incrementing by more than a unit the number of bits on which a selected command value is mapped, wherein a unit equals N-bits plus a plurality of additional bits. The N most significant bits of the selected command value are converted. The plurality of additional bits are decoded by generating a corresponding plurality of intermediate levels of variation in the duty cycle. Each intermediate level has a duration of half a clock period and produces a plurality of signals out of phase among each other by half a clock period. A driving PWM signal is generated by multiplexing the signals out of phase among each other by half a clock period, and carrying out logic combinations of these signals as a function of a most significant bit of the selected command value and as a function of the plurality of additional bits.

Conversion of a numeric command value in a constant frequency PWM drive signal for an electromagnetic load

The present invention relates to the positioning of the read/write transducer heads of an hard disk (HD) in a designated landing zone when requested or when the electrical power is removed from the drive. In particularly it relates to the detection of the back electromotive force (BEMF) of the motor involved in the positioning of the read/write transducer heads. According to an embodiment of the present invention a BEMF detection circuit for a voice-coil motor operative to continually generate a signal proportionally to the velocity of said voice-coil motor comprises a algebraic summing node producing at its output the BEMF of the voice-coil motor and receiving: a first voltage proportional to the voltage across the voice-coil motor; a second voltage representing the product of a first multiplier factor and a voltage proportional to the current in the coil; a third voltage representing the product of a prefixed bias voltage Vref and a second multiplier factor; said third voltage is calibrated by a single calibration circuitry operative to calibrate said second multiplier factor in response to a calibration control signal, in order to cancel said second voltage.

Calibration technique of a BEMF detector

A successive approximation shift register without redundancy for a finite-state machine of the sequential type, is also effective to store the machine states. The shift register comprises a chain of logic circuits of the bistable type (FF0,FF1, . . . ) having an input stage with selectable signal inputs which are feedback connected through logic OR gate circuits (OR0,OR1, . . . ,OR6).

Successive approximation and shift register without redundancy

A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

D flip-flop having asynchronous data loading

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Milan, Italy

Lorenzo Papillo