Marvellworld Trade Ltd.

National Semiconductor Corporation

Loren Tomasi

Nikhil Balram

Richard David Taylor

Vipin Namboodiri

Sanjay Saran Garg

Shilpi Sahu

Bipasha Ghosh

Gwyn Edwards

Kaip Sridhar

Richard Alexander Erhart

Mark Kuhns

Arif Alam

The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video signals and select some of their video signal portions for processing. The selection stage may time-multiplex some of the video signal portions. An analog to digital conversion stage may be shared by the time-multiplexing of the video signals. A decoder stage may decode the various signal portions and provide decoded output video signals. These feature may reduce the overall cost of the system. Various clock signals may be used to operate various stages of a multimode video decoder. Some of the clock signals may run at different frequencies and others may operate at a different phase.

Shared memory multi video channel display apparatus and methods

A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared within the signal processing circuitry. The sharing of some stored field lines reduces overall memory bandwidth and capacity requirements. The signal processing circuitry may be capable of performing multiple field line processing. A set of field line buffers may be provided to store field lines for multiple field segments and may provide the data to the corresponding inputs of the signal processing circuitry. To further reduce storage, some of the field line buffers may also be shared among the signal processing circuitry.

A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.

A method and circuit capable of handling skew between a clock and data signal up to +/&#x2212; one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first sampling region and in a second sampling region and determining a difference between a number of transitions in the first sampling region and a number of transitions in the second sampling region. The sampling regions and a deskew timing signal may then be incremented or decremented based on a comparison of the computed difference to a predetermined constant. If no transitions occur on a particular bit, the algorithm times out leaving the deskew timing signal in the original position. When analysis of a final bit of a channel is completed, the algorithm begins monitoring and analyzing the first bit of another channel.

Switched deskew on arbitrary data

A switched-capacitor programmable gain amplifier (PGA) has improved circuit performance that avoids impracticably small capacitors, while providing low total harmonic distortion (THD) and reasonable gain linearity. The sampling capacitor (CS) in the PGA is designed with a C-2C capacitor array. Gain settings from the C-2C capacitor array arranged for selection with constant VGS switches. The gain of the resulting PGA corresponds to the ratio of the effective capacitance of the C-2C array and the effective capacitance value of the feedback capacitor (CF). The resulting performance of the PGA has reduced charge injection and clock feed-through errors, and thus reduced THD.

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Chandler, AZ, United States of America

Loren Tomasi