Cypress Semiconductor Corporation

Nvx Corporation

Other

Loren T Lancaster

Ryan Tasuo Hirose

Krishnaswamy Ramkumar

Manuj Rathor

Fred B Jenne

Biju Parameshwaran

A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step), forming a charge storing dielectric (step), and forming a top insulating layer (step) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.

Method of manufacturing an oxide-nitride-oxide (ONO) dielectric for SONOS-type devices

A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step ), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step ), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step ).

Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices

A non-volatile memory IGFET device has a gate dielectric stack that is di lectrically equivalent to a layer of silicon dioxide having a thickness of to 170 &angst; or less. Above the dielectric stack is a polycrystalline silicon gate that is doped in an opposite manner to that of the source and drain regions of the transistor. By using a gate doping that is opposite to that of the IGFET source and drain regions the poly depletion layer that can occur during programming in modern and advanced memory devices is eliminated according to this invention. The device of this invention forms an accumulation layer in the poly rather than a depletion layer. This difference not only greatly improves the program speed, but allows for selecting the gate doping at levels as low as 10 /cm , or less, without significantly compromising the program speed. Further, since the majority of the applied voltage in a device according to this invention is dropped over the gate dielectric, rather than shared between the gate dielectric and a depletion layer in the gate poly, the device of this invention can be scaled in gate dielectric thickness without significantly compromising the program speed.

Semiconductor non-volatile memory device having an improved write speed

A semiconductor device and method of manufacturing a semiconductor device is disclosed in which a SONOS-type dielectric may include a charge storing dielectric (206) that includes at least one charge trapping dielectric layer (212) formed within. A charge trapping dielectric layer (212) may be a silicon-rich silicon nitride layer that may trap charge that could otherwise tunnel through a charge storing dielectric (206). A method may include forming a tunneling dielectric (302), forming a first portion of a charge storing layer (304-0), forming a charge trapping layer (306), forming a second portion of a charge storing layer (304-1), and forming a top dielectric (308).

Semiconductor device having silicon-rich layer and method of manufacturing such a device

A NAND stack array ( ) is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors ( ) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

Semiconductor non-volatile memory device having a NAND cell structure

A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a recall operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section. Means are provided for connecting the first circuit section and the second circuit section into a bistable configuration.

Semiconductor non-volatile latch device including non-volatile elements

A non-volatile memory IGFET device has a gate dielectric stack that is dielectrically equivalent to a layer of silicon dioxide having a thickness of 170 .ANG. or less. Above the dielectric stack is a polycrystalline silicon gate that is doped in an opposite manner to that of the source and drain regions of the transistor. By using a gate doping that is opposite to that of the IGFET source and drain regions, the poly depletion layer that can occur during programming in modern and advanced memory devices is eliminated according to this invention. The device of this invention forms an accumulation layer in the poly rather than a depletion layer. This difference not only greatly improves the program speed, but allows for selecting the gate doping at levels as low as 10.sup.11 /cm.sup.3, or less, without significantly compromising the program speed. Further, since the majority of the applied voltage in a device according to this invention is dropped over the gate dielectric, rather than shared between the gate dielectric and a depletion layer in the gate poly, the device of this invention can be scaled in gate dielectric thickness without significantly compromising the program speed.

A non-volatile semiconductor reference voltage source has a memory unit capable of storing information about a history of an associated circuit. The memory unit is located in proximity to the memory unit and contains at least some similar elements as the memory unit. The history may include information about at least some of the following: states of stored information, construction variations of the elements of the associated circuit, environmental considerations, deterioration and fatigue of the elements, and decay of information in the associated circuit. The memory unit is connected to modify an output of the reference voltage source in accordance with the stored information. A method is also presented for generating a reference voltage within an integrated memory circuit. The method includes providing a column of said memory units, each memory unit having a unique row line set associated with it. A low-side line of said additional column is isolated from substantial current sources or current sinks, and the low-side line of said additional column is charged to said reference voltage. The voltage on said low-side line of said additional column is provided to an output node when said charging is substantially complete.

Semiconductor reference voltage generator having a non-volatile memory

Semiconductor non-volatile device including embedded non-volatile

A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a power up operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section. Means are provided for connecting the first circuit section and the second circuit section into a bistable configuration.

Semiconductor non-volatile latch device including embedded non-volatile

A non-volatile memory cell array using only a single level of polysilicon and a single level of metal has programmable single transistor memory cells on a semiconductor substrate of a first conductivity type, a well of a second conductivity type in the substrate, parallel bitlines oriented in a first direction, and reference line segments oriented in the first direction. Each reference line is paired with one of each bitline. The array also has parallel word lines oriented in a second direction to form an array of intersections with the pairs of bitline/reference line pairs, and a rewriteable single transistor memory cell at each intersection point.

Single poly memory cell and array

A method and structure for preventing over erasure in non-volatile memory cells uses simultaneous erase and program current injections which offset one another. These currents come from two separate injection points within the non-volatile memory transistor and are dominant at different points during the erase operation. The first occurring current erases the non-volatile device and the second prevents over erasure.

Structure and method to prevent over erasure of nonvolatile memory

A semiconductor integrated circuit to determine a passage of time that may include a time during which no electrical power is supplied to the circuit is disclosed. The circuit has a timing device that includes a memory storage dielectric material for trapping charge carriers and releasing the trapped charge carriers in a known manner over time. The timing device has an electrical parameter that is relatable to an electric field created by the trapped charge carriers. A charge injection circuit is provided for selectively injecting charge carriers into the memory storage dielectric material to create an initialized state, and a time reader circuit determines when the electrical parameter has reached a predetermined value that corresponds to a passage of a predetermined time. Preferably the timing device is an insulated gate field effect transistor in which the memory storage dielectric material is a dielectric material, such as SONOS or SNOS, between the gate and channel overlying at least the channel area.

Integrated circuit timer function using natural decay of charge stored

A transistor structure (10), memory array (150) using the transistor structure, and method for making it are presented. The memory array (150), on a semiconductor substrate (152), contains a plurality of substantially parallel bit lines (154,155). A plurality of channel regions in the substrate (152) are bounded in one direction by a sets of bit line pairs (154,155). A conductive field shield layer (160), over a first insulation layer (156), is patterned to provide electrical regions over the channel regions between the first alternate sets of the bit lines (154,155) to form isolation transistor structures when biased with respect to the substrate (152). The field shield layer (160) is patterned to expose the channel regions of the memory transistors (151, . . . , 151'') between second alternate sets of the bit lines (155,154). A second insulating layer (163) is formed over the field shield layer (160). A nonvolatile memory dielectric layer (165) is formed over the channel regions between the second alternate sets of the bit lines (155,154). A conductive gate layer (166), patterned to provide a plurality of stripes, extends across the channel regions of the second alternate sets of bit lines (155,154). In one embodiment, the electrical regions patterned from the conductive field shield layer are a plurality of substantially parallel stripes overlying the channel regions between the first alternate sets of the bit lines, and may additionally overlie at least a portion of the bit lines of the first alternate sets of the bit lines. The plurality of stripes of the conductive gate layer are preferably substantially orthogonal to the parallel field shield stripes. In another embodiment, the field shield layer is substantially self aligned with the channel regions of the second alternate sets of bit lines in a direction orthogonal to the direction of current flow in the channels of the memory transistors (151, . . . , 151'').

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Colorado Springs, CO, United States of America

Loren T Lancaster