Freescale Semiconductor,inc.

Everspin Technologies, Inc.

Loren J Wise

Mark A Durlam

Eric John Salter

Gloria J Kerszykowski

Thomas V Meixner

Mitchell T Lien

Thomas Andre

Nicholas David Rizzo

Li Hsin Chang

Embodiments of a magnetoresistive random access memory (MRAM) array include multiple transistors having source and drain regions, and multiple substantially planar MRAM bits. The MRAM bits have upper and lower electrodes and intervening magnetics layers. The lower electrodes of at least some of the MRAM bits are formed substantially directly on at least some of the source or drain regions without an intervening via. Embodiments of an MRAM array also include a first conductive interconnect layer above and in electrical contact with the upper electrodes of at least some of the MRAM bits, with no metal layers intervening between the upper electrodes and the first conductive interconnect layer.

Space and process efficient MRAM

A memory device, such an MRAM device, includes self-healing reference bits () associated with a set of array bits (). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits () is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit () is toggled back to its original state.

Methods and apparatus for a memory device with self-healing reference bits

Methods and apparatus are provided for magnetoresistive random access memory (MRAM) bits (') combined with associated drive or sense transistors () to form an integrated MRAM array. The MRAM array has lower electrodes () of the MRAM bits (&#x2032;) formed substantially directly on a source or drain region (-) of associated drive or sense transistors (), so that the intervening vias () and underlying interconnects layers () of the prior art () can be eliminated. An interconnect layer () is provided above the MRAM bit (&#x2032;) and transistor () combination () for coupling upper electrodes () of the MRAM bits (&#x2032;) and other electrodes (----) of the transistors () to other elements of the array. Because the lower electrodes () of the MRAM bits (&#x2032;) are formed in substantial contact with the source or drain regions (--) of the transistors (), a separate interconnect layer () and/or via () for that purpose is not needed. As a consequence, the MRAM array is more space and process efficient.

Space and process efficient MRAM and method

A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating material. The implant may be a blanket or a targeted implant.

Method of manufacturing a magnetoelectronic device

Magnetoelectronic memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line disposed at least partially within a dielectric layer. The dielectric material layer overlies an interconnect stack. A void space is etched in the dielectric layer to expose the interconnect stack. A conductive-barrier layer having a first portion and a second portion is deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer is formed overlying the first portion and an electrode layer is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.

Magnetoresistive random access memory device structures and methods for fabricating the same

A magnetoresistive random access memory (MRAM) is embedded with another circuit type. Logic, such as a processing unit, is particularly well-suited circuit type for embedding with MRAM. The embedding is made more efficient by using a metal layer that is used as part of the interconnect for the other circuit also as part of the MRAM cell. The MRAM cells are all written by program lines, which are the two lines that cross to define a cell to be written. Thus, the design is simplified because there is commonality of usage of the metal line that is used for one of the program lines for the MRAM and for one of the interconnect lines for the logic.

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Tempe, AZ, United States of America

Loren J Wise