Intel Corporation

Other

Loren A Chow

Peter G Tolchinsky

Mantu K Hudait

Mohamad A Shaheen

Joel Mark Fastenau

Dmitri Loubychev

Amy W K Liu

Peter P Chow

Josephine N Lo

Jack T Kavalieros

Robert S Chau

Marko Radosavljevic

Matthew V Metz

Van H Le

Niloy Mukherjee

Benjamin Chu-Kung

Niti Goel

James M Powers

Mark R Lemay

Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby

A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1&#xd7;10cmto be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

Stacking fault and twin blocking barrier for integrating III-V on Si

Various embodiments provide a buffer layer that is grown over a silicon substrate that provides desirable device isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

Buffer layers for device isolation of devices grown on silicon

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an InAlAs bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InAlAs layer on the InAlAs bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.

Methods of forming buffer layer architecture on silicon and structures formed thereby

A device grade III-V quantum well structure formed on a silicon substrate using a composite buffer architecture and the method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1&#xd7;10cmto be formed on silicon substrates. In an embodiment of the present invention, an InSb quantum well layer is sandwiched between two larger band gap barrier layers. In an embodiment of the present invention, InSb quantum well layer is strained. In a specific embodiment, the two larger band gap barrier layers are graded.

Dislocation-free InSb quantum well structure on Si using novel buffer architecture

Various embodiments proved a buffer layer that is grown over a silicon substrate that provides desirable isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

An assembly comprising a semiconductor substrate having a first lattice constant, an intermediate layer having a second lattice constant formed on the semiconductor substrate, and a virtual substrate layer having a third lattice constant formed on the intermediate layer. The intermediate layer comprises one of a combination of III&#x2013;V elements and a combination of II&#x2013;VI elements. The second lattice constant has a value that is approximately between the values of the first lattice constant and the third lattice constant.

III-V and II-VI compounds as template materials for growing germanium containing film on silicon

An apparatus including a contact point formed on a device layer of a circuit substrate or interconnect layer on a substrate; a first dielectric layer including cubic boron nitride on the substrate; and a different second dielectric layer on the substrate and separated from the device layer by the first dielectric layer. Also, an apparatus including a circuit substrate including a device layer and a composite dielectric layer. The composite dielectric includes a first dielectric material including cubic boron nitride and a different second dielectric material. The first dielectric material surrounds the second dielectric material.

Composite dielectric layers

An apparatus including a contact point on a substrate; a first dielectric layer comprising a material having a dielectric constant less than five formed on the contact point, and a different second dielectric layer formed on the substrate and separated from the contact point by the first dielectric layer. Collectively, the first and second dielectric layers comprise a composite dielectric layer having a composite dielectric constant value. The contribution of the first dielectric layer to the composite dielectric value is up to 20 percent. Also, a method including depositing a composite dielectric layer over a contact point on a substrate, the composite dielectric layer comprising a first material having a dielectric constant less than 5 and a second different second material, and forming a conductive interconnection through the composite dielectric layer to the contact point.

A gaseous deposition source for providing a deposition material that emanates from a crucible having multiple thin film heating elements formed thereon, with each adjacent pair being separated by an insulating layer therebetween. A gaseous deposition source can have a crucible with a cover thereon with one or more apertures therein and with thin film heating elements on that cover about such apertures. A substrate heater may be used formed of thin film heating elements provided on a base.

Deposition heaters

A gaseous deposition source for providing a deposition material that emanates from a crucible having mulitple thin film heating elements formed thereon, with each adjacent pair being separated by an insulating layer therebetween. A gaseous deposition source can have a crucible with a cover thereon with one or more apertures therein and with thin film heating elements on that cover about such apertures. A substrate heater may be used formed of thin film heating elements provided on a base.

A needle shielding device attachable to a hypodermic syringe for protecting a user from contacting the tip of a needle. The device comprises a generally cylindrical needle shield slidably engaging a syringe body for protecting a user from being stuck by the needle tip of the syringe. The needle shield continuously frictionally engages and grips the syringe body as the shield is moved between a retracted position wherein the needle extends forwardly of the needle shield and a extended position wherein the needle tip is protectively enclosed by the needle shield.

Hypodermic syringe with needle shield

A puncture protector having a flexible backing with adhesive on one side thereof and a shielding arrangement for blocking passage of needles, both of which can be conformed to that portion of the body of the needle user, often the fingers, which is desired to be protected.

Growing community of inventors

Santa Clara, CA, United States of America

Loren A Chow