International Business Machines Corporation

Lonny Lambrecht

Jeffrey A Stuecheli

Paul Allen Ganfield

Melissa Ann Barnum

Charles Francis Marino

Robert Christopher Dixon

Michael Steven Siegel

Philip Heidelberger

Cyriel Johan Minkenberg

Kent Harold Haselhorst

Mark David Bellows

Tolga Ozguner

Daniel Ramirez

Bogdan Prisacari

Wolfgang Emil Denzel

German Rodriguez Herrera

Christopher Jon Johnson

David M Kauer

Zelun Tie

Baba L Arimilli

William John Starke

Daniel Mark Dreps

Lakshminarayana Baba Arimilli

Bartholomew Blaner

John David Irish

Kenneth Michael Valk

David John Krolak

Curtis Carl Wollbrink

Yiftach Benjamini

William John Goetzinger

Merwin Herscher Alferness

Joshua W Rensch

William S Starke

An integrated circuit includes a transmitting circuit configured to be coupled to a physical serial interface having a bit width. The transmitting circuit is configured to transmit, via the physical serial interface, a frame including multiple aligned flits all of an equal fixed length that is an integer multiple of the bit width of the physical serial interface. The multiple flits include both a control flit specifying at least a command to be performed by a recipient of the command and a data flit providing data to be operated upon through performance of the command. The control flit includes a data protection code computed over the control flit and a data flit of a previously transmitted frame.

Frame format for a serial interface

A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.

Pre-transmission data reordering for a serial interface

A multiprocessor computer system includes a plurality of processor nodes and at least a three-tier hierarchical network interconnecting the processor nodes. The hierarchical network includes a plurality of routers interconnected such that each router is connected to a subset of the plurality of processor nodes; the plurality of routers are arranged in a hierarchy of n&#x2267;3 tiers (T, . . . , T); the plurality of routers are partitioned into disjoint groups at the first tier T, the groups at tier Tbeing partitioned into disjoint groups (of complete Tgroups) at the next tier Tand a top tier Tincluding a single group containing all of the plurality of routers; and for all tiers 1&#x2266;i&#x2266;n, each tier-Tsubgroup within a tier Tgroup is connected by at least one link to all other tier-Tsubgroups within the same tier Tgroup.

Interconnection network topology for large scale high performance computing (HPC) systems

A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is determined that the second processor can be communicated with via a first bidirectional communication path. It is determined that bandwidth is available on the first bidirectional communication path. It is determined that bandwidth is available on a second bidirectional communication path. In response to a determination that bandwidth is available on the second bidirectional communication path, a data path is created between the first component and the second bidirectional communication path and the request to send the message to the second component is granted. In response to a determination that bandwidth is not available on the first bidirectional communication path or on the second bidirectional communication path, the grant of the request to send the message to the second component is delayed.

Intercomponent data communication between different processors

A request to send a first message from a first component to a second component is received at an arbiter. The first component is located in a first time zone and the second component is located in a second time zone. The arbiter determines that the second component is located in the second time zone. It is determined that the second time zone can be communicated with via one or more communications channels in a first direction. It is determined whether bandwidth is available on the one or more communications channels in the first direction. If bandwidth is available on the one or more communications channels in the first direction, a data path between the first component and the one or more communications channels in the first direction is created and the request is granted. Otherwise, the grant of the request is delayed.

Intercomponent data communication

Intercomponent data communication between multiple time zones

A computer-implemented method includes storing commands and maintaining an order of receipt of the commands in a command processing unit. The commands include address translation cache miss commands that are organized as one or more linked lists and stored in a content-addressable memory (CAM). All nodes within a single linked list include commands having addresses that map to the same hash value. Based on receiving a memory fetch completion indicator for a cache entry for a command in a head node in a linked list, all of the commands in the linked list are returned. The returning includes sending the commands in the linked list to an address translation unit in an order specified by the linked list.

Maintaining command order of address translation cache misses and subsequent hits

In a first aspect, a first method is provided for self-adjusting allocation of memory bandwidth in a network processor system. The first method includes the steps of (1) determining an amount of memory bandwidth of a network processor used by each of a plurality of data types; and (2) dynamically adjusting the amount of memory bandwidth allocated to at least one of the plurality of data types based on the determination. Numerous other aspects are provided.

Methods and apparatus for allocating bandwidth for a network processor

The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Memory controller operating in a system with a variable system clock

Separate handling of read and write operations of Read-Modify-Write Commands in an XDR&#x2122; memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

Separate handling of read and write of read-modify-write

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Byron, MN, United States of America

Lonny Lambrecht