Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Nxp B.v.

Vns Portfolio LLC

4 Peaks Technology LLC

Philips Electronics North America Corporation

4 Peak Technology LLC

Lonnie Calvin Goff

David R Evoy

Peter Chambers

Mark Eidson

Franklyn H Story

Brian Logsdon

Michael Richard Conley

Gary D Hicok

Joseph Alan Thomsen

Gary A Walker

Gabriel R Munguia

Steve Cornelius

James C Steele

Mark Sullivan

Menno Menasshe Lindwer

Bonnie Collett Sexton

Edward Michael Petryk

Steven E Cornelius

Bruce E Cairns

Mark Hidson

A cell balancing software program that executes on a computer system embedded inside a multi-cell battery and includes a means to control an external charging system. When a charge imbalance is detected between the cells, a cell balancing algorithm is selected from a plurality of cell-balancing algorithms and is executed. The executed algorithm causes a charge request, which specifies desired charging parameter(s), to be generated, and the charge request is transmitted to the external charging system. After the external charging system charges the battery according to the charge request, the effectiveness of the cell-balancing algorithm can be evaluated and stored in a history. The history can be used to select cell balancing algorithm(s) for future cell balancing.

Integrated cell balancing system, method, and computer program for multi-cell batteries

A computer system that installs in the proximity of the vehicle's operator, attaches to the battery power source in the vehicle's wiring harness, gathers information relating to the operational state of the vehicle's battery, calculates the health of the battery from the gathered information, provides the health and operational state of the battery to the vehicle's operator and can include the means for supporting non-battery related functions.

Battery monitor system attached to a vehicle wiring harness

A system for monitoring the starter battery of a vehicle includes a central processing unit, a voltage sensor, a temperature sensor, a timer, a data store, and a display. A collection of computer software algorithms are executed by the central processing unit to ascertain the operational state of a vehicle's starter battery. The algorithms are operative to determine engine start time, initial start voltage drop, and the charge state of the battery.

Battery monitoring algorithms for vehicles

A computer arrayincluding a field of processors-each processor having a separate memory. The processors-are connected to their immediate neighbors with links. Several configurations of the links are described including differing types of data linesand control lines. Along linesProcess Command Words (PCW) to initiate processing tasks and Routing Connection Words (RCW) to initiate routing tasks pass between the processors-to provide a method for altering the mode of hybrid processors-in the array.

Method and apparatus for using port communications to switch processor modes

A technique is provided for configuring and controlling complex hardware subsystems that relieves the burden placed on the system programmer and that is, by comparison to present methods, safe and error-free. In accordance with one aspect of the invention, configuration of a hardware subsystem () is accomplished by providing in hardware a configuration controller including a controller portion () and a storage portion () storing configuration parameters. The configuration controller () is activated, for example in response to a Configuration/Control ID, and thereupon performs configuration of the hardware subsystem (), including storing at least one configuration parameter in a register () of the hardware subsystem. Typically, the configuration controller hardware () and storage () are embedded within the hardware subsystem to be configured or controlled. The configuration/control functionality is thus 'encapsulated' within the hardware subsystem () itself such that the system programmer need not be concerned with details.

Encapsulated hardware configuration/control

A ring oscillator comprises a control circuit for receiving a frequency-selection signal operative to select from at least two ring oscillator frequencies, said control circuit using said control signal to generate a first control signal and a second control signal; a primary chain of an odd number of serially connected NOT gates, said primary chain including a primary switching NOT gate responsive to the first control signal and operative to perform a logical NOT or an IGNORE function on a first oscillating input signal to generate a first output signal; and a secondary chain of serially connected NOT gates, said secondary chain logically parallel to at least said primary switching NOT gate, said secondary chain including a secondary switching NOT gate responsive to the second control signal and operative to perform a logical NOT or an IGNORE function on a second oscillating input signal to generate a second output signal.

Multi-speed ring oscillator

A computer-based software task management system includes an index register configured to store a data register pointer for pointing to a data register. A Task ID register is coupled to the index register and configured to store a Task ID keyed to the index register. A Task ID memory is coupled to the Task ID register and configured to store a flag indicating whether the Task ID is available. A state machine is coupled to the Task ID memory and configured to allocate Task IDs on an available basis using a task ID memory.

Hardware register access via task tag ID

Among the embodiments of the present invention is a technique that includes executing a first protocol on test bus () in accordance with an established test standard to operate a first topology of several test ports () and activating to a shadow controller () by executing a second protocol on test bus (). Operation of the test ports () is suspended during execution of the second protocol. During activation, the shadow controller () can be used to set-up a second topology of one or more of test ports () for operation after the test port suspension is discontinued.

Test circuit topology reconfiguration and utilization techniques

An array boundary checking method is disclosed for providing hardware based array boundary checking in a Java environment. During the first machine cycle of a current array access command, an array reference value is loaded into a system-data address controller and an array boundary checker. Next, during the second machine cycle of the current array access command, an array index value is written to the system-data address controller and the array boundary checker. Also during the second machine cycle of the current array access command, a maximum array index value is read from the Java array and written to the array boundary checker. The array boundary checker utilizes these values to determine the validity of the current array access command. Finally, during the third machine cycle an array value is accessed in memory. In the present invention the array value is only accessed when the current array access command is valid.

System and method for low overhead boundary checking of java arrays

A power management method is disclosed which provides power management for a hardware based Java accelerator. Initially, a Java mode signal is provided from a host processor in response to initiating a Java application. Thereafter, power to the host processor is reduced, and power to a Java processor is increased in response to the Java mode signal. Then, when execution of the Java application halts, a Java completion signal is generated from the Java processor, thus signaling the system to return control back to the host processor.

System and method for power management in a Java accelerator environment

A method and apparatus for supporting a host computer system in executing a JAVA computer program. An auxiliary system, including multiple non-host processors, coupled to a non-host memory, via a bus to the host computer system, interfaces with a JAVA Virtual Machine (JVM) to execute one or more threads of the JAVA computer program. The JVM can be instantiated in the non-host memory. The JVM performs allocation of an additional non-host processor for interfacing with the JVM to execute the new thread. The auxiliary system need not be a permanent part of the host computer system. In one embodiment the auxiliary system is coupled to the host computer system to run JAVA programs. The auxiliary system can be detached from the host computer system or can be implemented as a permanent part of the host computer system.

Multi-processor JAVA subsystem

Among the embodiments of the present invention is a processor ( ) having a number of registers in a register bank ( ). The registers include a general purpose register ( ) and a stack pointer register ( ) having a common register name. Processor ( ) includes logic responsive to programming to perform a program instruction that references the common register name. This instruction is performed with general purpose register ( ) under a first condition and with stack pointer register ( ) under a second condition. Accordingly, multiple registers identified by the same name can be selectively accessed based on the establishment of certain conditions.

Selective access to multiple registers having a common name

Among the embodiments of the present invention is test equipment ( ) to test an integrated circuit ( ). The integrated circuit ( ) includes one or more processors and one or more communication devices ( ). The test equipment ( ) includes a responder integrated circuit ( ) that has at least one processor, several communication devices ( ), and one or more configuration connections ( ). The responder integrated circuit responds to commands from the first integrated circuit ( ) and a configuration established with the one or more configuration connections ( ) to test operation of the one or more communication devices ( ).

Multi-environment testing with a responder

A hybrid one time pad encryption and decryption apparatus with methods for encrypting and decrypting data wherein a one time random number pad provides high security encryption. The random number sequence is encrypted using DES, RSA or other technique and embedded in the message as a function of the random pad itself. This generates an encryption message that is impervious to attempts to directly decode the message text as the message is randomly dispersed throughout a message and the message contains as much quasi-random data as text. The message is also relatively impervious to attempts to decode the cipher, as the cipher is randomly interrupted by the encrypted data.

Hybrid one time pad encryption and decryption apparatus with methods for encrypting and decrypting data

A cryptographic device includes a de-multiplexer, a plurality of encryption blocks, a plurality of permutation blocks, and a multiplexer. The encryption blocks encrypt data to produce encrypted data. The de-multiplexer receives data portions from a plaintext message and directs the data portions to one of the encryption blocks, based on a value within a path control session key. Each permutation block is associated with an encryption block. Each permutation block permutes encrypted data from the encryption block associated therewith. The multiplexer receives data portions from each of the plurality of permutation blocks to produce an encrypted output data stream.

Growing community of inventors

Tempe, AZ, United States of America

Lonnie Calvin Goff