Southeast University

Csmc Technologies Fab2 Co., Ltd.

Longxing Shi

Weifeng Sun

Siyang Liu

Shengli Lu

Shen Xu

Jun Yang

Qinsong Qian

Weiwei Shan

Jing Zhu

Long Zhang

Sheng Li

Wei Su

Chi Zhang

Sen Zhang

Qi Liu

Jiaxing Wei

Na Bai

Hao Wang

Peng Cao

Jie Ma

Bo Liu

Xinning Liu

Dejin Wang

Kui Xiao

Jinyu Xiao

Hong Li

Shaojun Wei

Leibo Liu

Feng Lin

Shouyi Yin

Yuan Chen

Jianhui Wu

Meng Zhang

Hong Chang

Yifeng Deng

Youshan Jin

Yingcheng Xia

Zhiyi Ye

Miao Yang

Sichao Liu

Ningbo Li

Fei Pan

Xinyi Tao

Minggang Chen

Yujie Liu

Guiqiang Zheng

Qiang Luo

Siyu Zhao

Shengyou Xu

Jinjiang Yang

Ziyan Zhou

Jiafeng Zhu

Yue Feng

Cai Gong

Yuan Gao

Wei Dong Wang

Haisong Li

Chong Wang

Yangbo Yi

Yan Gu

Chao Chen

Yang Zhang

Zixuan Wang

Chao Liu

Nailong He

Jie Li

Wei Zhao

Wei Ge

Chen Hu

Jie Sun

Lixuan Zhu

Congming Qi

Li Lu

Bowei Yang

Danhong Gu

Siyuan Yu

Junhui Gu

Ankang Li

Rongrong Tao

Yangyang Lu

Dahai Hu

Xianguo Huang

Haolin Gu

Xuexiang Wang

Tao Zhao

Changlong Huo

Yu Gong

Shaohong Li

Guichuang Zhu

Yunwu Zhang

Boyong He

Kuo Yu

Rui Jiang

Wanqing Yang

Menglin Yu

Wentao Dai

Hu Zhang

Huaxin Zhang

An inductor current estimation method for a DC-DC switching power supply using a voltage sampling module, a data conversion module, a switching signal counting module, an inductor voltage calculation module and a digital filter module, comprising: processing an input voltage and an output voltage by the voltage sampling module and the data conversion module to obtain a converted input voltage and a converted output voltage which have a same number of bits; comparing a node voltage with a reference voltage, and then obtaining a duty cycle by the switching signal counting module; and then, outputting an average voltage of two terminals of an inductor and a parasitic resistor by the inductor voltage calculation module, and finally, obtaining an estimated inductor current by the digital filter module.

Inductor current estimation method for DC-DC switching power supply

A conductive channel structure for SiC devices, a fully integrated SiC device and a fully integrated manufacturing process thereof are provided. The fully integrated SiC device features a low-voltage region, a first high-voltage region and a second high-voltage region separated by isolation structures on the same SiC-based chip, and integrates first and second conductivity type MOS devices. The first and second conductivity type devices employ first and second conductivity type conductive channels respectively with alternating N-type and P-type first or second conductivity type areas above them. The manufacturing process includes sequentially stacking a second conductivity type epitaxial layer and buffer layer on an N-type substrate; and within the second conductivity type buffer layer, arranging first conductivity type well regions, heavily doped regions, channel regions, second conductivity type well regions, isolation structures, heavily doped regions, and channel regions.

Conductive channel structure for SiC devices, fully integrated SiC device and fully integrated manufacturing process thereof

A horizontal Hall device includes a substrate layer and a BOX layer arranged on the substrate layer, where an epitaxial layer is arranged on the BOX layer, a well layer is arranged on the epitaxial layer, an STI layer is arranged on the well layer, a pair of induction electrodes and a pair of bias electrodes are arranged on the STI layer, ground electrodes are arranged on the epitaxial layer, and current barrier layers are arranged between the induction electrodes and the adjacent bias electrodes.

Horizontal hall device and preparation method

A non-isolated resonant gate drive circuit includes a PMOS drive network, an NMOS clamping circuit and an inductor. The PMOS drive network and the NMOS clamping circuit are connected in parallel to two terminals of the inductor. Input signals of the PMOS drive network are provided by a function generator connected to a drive chip, drive signals are output via an output port vand an output port vafter the input signals are processed by the PMOS drive network, the NMOS clamping circuit and the inductor, the NMOS clamping circuit is used for controlling the state of the output port vand the output port vto change, and the inductor forms LC resonance together with a gate capacitor Cand a gate capacitor Cin the NMOS clamping circuit to recover energy in a process of turning off the drive circuit.

Non-isolated resonant gate drive circuit

A power semiconductor device includes: a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

Power semiconductor device and manufacturing method therefor

The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under 'negative margin', the system can further lower voltage, compress the timing slack, and obtain higher power gain.

Ultra low-power negative margin timing monitoring method for neural network circuit

An adaptive load optimization method for a resonant gate drive circuit is provided to optimize the switching loss, turn-on loss and gate drive loss under different MOSFET loads. A data table is pre-stored in a digital signal processor chip (DSP), and voltages and pre-charge times, corresponding to a low total loss, of the resonant gate driver obtained by actual tests in case of different load currents are recorded in the data table; and in actual application, after an analog-to-digital converter terminal (ADC) samples a load current, a load current, closest to the sampled load current, is read from the data table, and the digital signal processor chip (DSP) is enabled to perform table look-up to obtain an optimized voltage and pre-charge time of a gate drive circuit.

Adaptive load optimization method for resonant gate drive circuit

An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

Insulated gate bipolar transistor

The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.

High-threshold power semiconductor device and manufacturing method thereof

A control method for a four-switch buck-boost converter is provided. The control method adopts four-stage control, and divides the load range into two sections and adopts different control strategies according to a critical load value corresponding to optimal control. In Boost mode, before the critical load, Tand Tare kept constant, Tis a minimum value for realizing soft-switching, and Tdecreases with the increase of the load; when the critical load is reached, Tdrops to 0; and after the critical load, T, T, Tand T increase with the load. In Buck mode, before the critical load, Tand Tare kept constant, Tis a minimum value for realizing soft-switching, and Tdecreases with the increase of the load; when the critical load is reached, Tdrops to 0; and after the critical load, T, T, Tand T increase with the load.

Control method for four-switch buck-boost converter

An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

Enhancement-mode N-channel and P-channel GaN device integration structure

In the monolithically integrated GaN-based half-bridge circuit, a nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially provided on a conductive substrate, the barrier layer and the channel layer are separated by isolation layers, and a diode, an integrated capacitor, a low-side transistor, a high-side transistor, a first integrated resistor and a second integrated resistor are provided. The half-bridge circuit includes: a low-side transistor and a high-side transistor, wherein a drain of the low-side transistor is connected to a source of the high-side transistor and also connected to an output terminal Vout, and a substrate of the low-side transistor is connected to a substrate of the high-side transistor, wherein a series resistor is connected in parallel to a drain of the high-side transistor and a source of the low-side transistor.

Monolithically integrated GaN-based half-bridge circuit and half-bridge circuit

A multi-phase high-precision current sharing control method applied to constant on-time control is provided, wherein a current difference between continuously sampled current of each line and mean current is processed by a PI compensation module and a low-pass filter module to obtain on-time regulation data. A high bit of the regulation data controls the value of counter reference Vin an on-time control module, and a low bit controls the length of an enabled delay line in a delay line module. The counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of a DPWM. The method takes COT control of a Buck converter as a typical application. Compared with a multi-phase COT controller without a current-sharing mechanism, the method can improve the stability and reliability of the system.

Multi-phase high-precision current sharing control method applied to constant on-time control

A GaN power semiconductor device integrated with a self-feedback gate control structure comprises a substrate, a buffer layer, a channel layer and a barrier layer. A gate control area is formed by a first metal source electrode, a first P-type GaN cap layer, a first metal gate electrode, a first metal drain electrode, a second P-type GaN cap layer and a second metal gate electrode. An active working area is formed by the first metal source electrode, a third P-type GaN cap layer, a third metal gate electrode, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode. The overall gate leaking current of the device is regulated by the gate control area, the integration level is high, the parasitic effect is small, and the charge-storage effect can be effectively relieved, thus improving the threshold stability of the device.

GaN power semiconductor device integrated with self-feedback gate control structure

A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.

Synchronous rectification control system and method for quasi-resonant flyback converter

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Jiangsu, China

Longxing Shi