Huazhong University of Science and Technology

Zhejiang Lab

Long Zheng

Hai Jin

Xiaofei Liao

Qinggang Wang

Fan Zhang

Yu Huang

Haikun Liu

Zhiyuan Shao

Pengcheng Yao

Chengbo Yang

Xi Ge

Zhaozeng An

Ao Hu

Qingxiang Chen

The present invention relates to a hardware accelerator for hypergraph processing and its operating method, the hardware accelerator comprising: a data loader: for, in the presence of a data-centric load-trigger-reduce execution model, reading hypergraph partition data from an off-chip memory successively according to hypergraph data structure and an order of hypergraph partitions; an address translator, for deploying the hypergraph data into a private register of a processor and/or into a buffer memory according to a priority level of loaded data, and recording corresponding offset information; a task trigger, for generating computing tasks according to the loaded data, and scheduling the computing tasks into the processor; the processor, for receiving and executing the computing tasks; a reducer, for scheduling intermediate results into a first-priority-data reducer unit or a second-priority-data reducer unit depending on the priority level of the data so as to execute a reducing operation for the intermediate results. In view of the shortcomings of task-centric hardware accelerators, the present invention can prevent any possible data conflict during parallel execution of multiple processing units.

Hardware accelerator for hypergraph processing and operating method thereof

The present invention relates to a dynamic memory management apparatus and method for HLS, the apparatus has several searching and caching modules and several modifying and writing-back modules, the searching and caching modules are in connection with a DRAM storing module and a BRAM buffer, respectively, and the modifying and writing-back modules are in connection with the DRAM storing module and the BRAM buffer, respectively, the BRAM buffer is for caching information about nodes on a search path and registering information about modification made to the nodes. To remedy the defect that the traditional operating system is directly transplanted to the FPGA and has low execution efficiency, the present invention utilizes the advantage of the large capacity of the DRAM on the FPGA to realize efficient dynamic memory allocation and deallocation, and improve the usability and code reusability of HLS.

Dynamic memory management apparatus and method for HLS

A deep learning heterogeneous computing method based on layer-wide memory allocation, at least comprises steps of: traversing a neural network model so as to acquire a training operational sequence and a number of layers L thereof; calculating a memory room Rrequired by data involved in operation at the ilayer of the neural network model under a double-buffer configuration, where 1&#x2264;i&#x2264;L; altering a layer structure of the ilayer and updating the training operational sequence; distributing all the data across a memory room of the CPU and the memory room of the GPU according to a data placement method; performing iterative computation at each said layer successively based on the training operational sequence so as to complete neural network training.

Deep learning heterogeneous computing method based on layer-wide memory allocation and system thereof

The present invention relates to an optimization method for graph processing based on heterogeneous FPGA data streams. The method can balance processing loads between the CPU processing module and the FPGA processing module during acceleration of graph data processing.

Optimization method for graph processing based on heterogeneous FPGA data streams

A graph processing optimization method that addresses the problems such as the low computation-to-communication ratio in graph environments, and high communication overhead as well as load imbalance in heterogeneous environments for graph processing. The method reduces communication overhead between accelerators by optimizing graph partitioning so as to improve system scalability.

Graph processing optimization method based on multi-FPGA accelerator interconnection

An FPGA-based graph data processing method is provided for executing graph traversals on a graph having characteristics of a small-world network by using a first processor being a CPU and a second processor that is a FPGA and is in communicative connection with the first processor, wherein the first processor sends graph data to be traversed to the second processor, and obtains result data of the graph traversals from the second processor for result output after the second processor has completed the graph traversals of the graph data by executing level traversals, and the second processor comprises a sparsity processing module and a density processing module, the sparsity processing module operates in a beginning stage and/or an ending stage of the graph traversals, and the density processing module with a higher degree of parallelism than the sparsity processing module operates in the intermediate stage of the graph traversals.

FPGA coprocessor with sparsity and density modules for execution of low and high parallelism portions of graph traversals

The present invention relates to a graph-computing-oriented heterogeneous in-memory computing apparatus, comprising a memory control unit, a digital signal processing unit, and a plurality of analog signal processing units using the memory control unit.

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Hubei, China

Long Zheng