Southeast University

Qilu Pharmaceutical Co., Ltd.

Ge Precision Healthcare LLC

Jiangsu Hengrui Medicine Company Ltd.

Csmc Technologies Fab2 Co., Ltd.

Medshine Discovery Inc.

Antares Advanced Test Technologies (suzhou) Limited

Long Zhang

Longxing Shi

Weifeng Sun

Siyang Liu

Jie Ma

Minghui Zhang

Chuanwen Fan

Lei Xia

Jing Zhu

Guiqiang Zheng

Shousheng Yan

Shuhui Chen

Jingyi Wang

Sen Zhang

Jun Hou

Jian Li

Shengli Lu

Yan Gu

Zhaozhong Ding

Jianfei Wang

Yang Zhang

Jing Zhang

Xile Liu

Zhenjun Qiu

Haiwen Wan

Jianrong Zhu

Zongru Guo

Baoping Zhao

Peng Zhang

Yuan Gao

Yongxing Cao

Qingmin Yang

Yingying Yang

Zhantao Zhang

Shaobo Yang

Xiangyu Hou

Yong Gu

Jinrong Chen

Chunli Zhuo

Yichen Li

Xueqi Li

Kai Shen

Peigang Liu

Guobing Feng

Chengwu Pan

Ankang Li

Jinli Gong

Chao Xie

Chengzuo Cai

Yangguang Yuan

Yidong Zhu

Qingmei Zheng

Shansong Zheng

Jinqing Hu

Haojie Zhou

Dong Lin

Boyan Xu

Zhongru Guo

Ying Li

A conductive channel structure for SiC devices, a fully integrated SiC device and a fully integrated manufacturing process thereof are provided. The fully integrated SiC device features a low-voltage region, a first high-voltage region and a second high-voltage region separated by isolation structures on the same SiC-based chip, and integrates first and second conductivity type MOS devices. The first and second conductivity type devices employ first and second conductivity type conductive channels respectively with alternating N-type and P-type first or second conductivity type areas above them. The manufacturing process includes sequentially stacking a second conductivity type epitaxial layer and buffer layer on an N-type substrate; and within the second conductivity type buffer layer, arranging first conductivity type well regions, heavily doped regions, channel regions, second conductivity type well regions, isolation structures, heavily doped regions, and channel regions.

Conductive channel structure for SiC devices, fully integrated SiC device and fully integrated manufacturing process thereof

A horizontal Hall device includes a substrate layer and a BOX layer arranged on the substrate layer, where an epitaxial layer is arranged on the BOX layer, a well layer is arranged on the epitaxial layer, an STI layer is arranged on the well layer, a pair of induction electrodes and a pair of bias electrodes are arranged on the STI layer, ground electrodes are arranged on the epitaxial layer, and current barrier layers are arranged between the induction electrodes and the adjacent bias electrodes.

Horizontal hall device and preparation method

The disclosed semiconductor testing socket comprises a testing socket body, a guiding frame, and a height adjusting mechanism. The guiding frame is mounted above the testing socket body and is provided with a central insertion opening. The height adjusting mechanism is embedded at the edges of the central insertion opening. The height adjusting mechanism comprises an operable part that can be operated and a movable part that can be moved between a first position located outside the central insertion opening and a second position located within the central insertion opening by operating the operable part. The movable part comprises a supporting surface configured for supporting a specimen to be tested when located at the second position.

Semiconductor testing socket

An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

Insulated gate bipolar transistor

Display device

An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

Enhancement-mode N-channel and P-channel GaN device integration structure

In the monolithically integrated GaN-based half-bridge circuit, a nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially provided on a conductive substrate, the barrier layer and the channel layer are separated by isolation layers, and a diode, an integrated capacitor, a low-side transistor, a high-side transistor, a first integrated resistor and a second integrated resistor are provided. The half-bridge circuit includes: a low-side transistor and a high-side transistor, wherein a drain of the low-side transistor is connected to a source of the high-side transistor and also connected to an output terminal Vout, and a substrate of the low-side transistor is connected to a substrate of the high-side transistor, wherein a series resistor is connected in parallel to a drain of the high-side transistor and a source of the low-side transistor.

Monolithically integrated GaN-based half-bridge circuit and half-bridge circuit

Provided is a preparation method for a tyrosine kinase inhibitor and an intermediate thereof. Specifically, a preparation method for a cyanoquinoline compound is provided. The method has a high yield, good product purity, and mild reaction conditions.

Preparation method for tyrosine kinase inhibitor and intermediate thereof

A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.

Lateral insulated gate bipolar transistor with low turn-on overshoot current

Medical diagnostic equipment

Disclosed are two axially chiral isomers and pharmaceutically available salts thereof, preparation method therefor, and pharmaceutical use of the two axially chiral isomers or pharmaceutical compositions thereof.

Axially chiral isomers, and preparation methods therefor and pharmaceutical uses thereof

Disclosed is a spirocyclic aryl phosphorus oxide or sulfide as an ALK inhibitor, particularly, a compound represented by formula (I) as an ALK inhibitor or pharmaceutically acceptable salt thereof. 

Spirocyclic aryl phosphorus oxide and aryl phosphorus sulfide

The present invention relates to 4-(substituted anilino)-quinazoline derivatives as tyrosine kinase inhibitors. Specifically, compounds of formula I, or pharmaceutically acceptable salts or solvates thereof are disclosed, in which each substitutent in formula I is defined in the description. Preparation method of the compounds of formula I, pharmaceutical compositions and pharmaceutical uses thereof are also disclosed. The compounds of formula I are effective tyrosine kinase inhibitors. 

4-(substituted anilino)-quinazoline derivatives useful as tyrosine kinase inhibitors

Provided are pyrrolyl substituted dihydroindol-2-one derivatives represented by formula (I), pharmaceutically acceptable salts or solvates of said derivatives, or solvates of said salts, which are effective tyrosine kinase inhibitors. Also provided are the preparation methods of the above compounds, pharmaceutical compositions containing these compounds, and the use of these compounds in manufacturing drugs useful for the treatment or adjunctive treatment of tumors medicated by tyrosine kinases or proliferation or migration of tumor cells driven by tyrosine kinases in mammals (including human). 

Pyrrolyl substituted dihydroindol-2-one derivatives, preparation methods and uses thereof

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Jiangsu, China

Long Zhang