Taiwan Semiconductor Manufacturing Comp. Ltd.

Long-Shang Juang

An-Min Chiang

Jyh-Feng Lin

Chi-Shiang Lee

A process for fabricating a flash EEPROM device, incorporating a shallow, heavily doped, source side region, used to improve the endurance of the flash EEPROM device, has been developed. The process features placing a shallow, ion implanted arsenic region, in the semiconductor substrate, adjacent to one side of a floating gate structure, prior to creation of the control gate structure. The addition of the shallow, ion implanted arsenic region, improves the coupling ratio at the source, which in turn results in the ability of the flash EEPROM device to sustain about 1,000,000 program/erase cycles, compared to counterparts, fabricated without the shallow, source side region, only able to sustain about 400,000 program/erase cycles.

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Tainan District, Taiwan

Long-Shang Juang