Alpha and Omega Semiconductor International LP

Alpha and Omega Semiconductor (cayman) Ltd.

Marvellworld Trade Ltd.

Integrated Device Technology, Inc.

Silicon Storage Technology, Inc.

Alpha and Omega Semiconductor (cayman) Ltd. Grand

Long-Ching Wang

Yan Xun Xue

Madhur Bobde

Kai Chen

Xiaotian Zhang

Jun Lu

Yueh-Se Ho

Zhiqiang Niu

Pei-Lun Huang

Yu-Ming Chen

Tien-Chi Lin

Jung-Pei Cheng

Yueh-Ping Yu

Shuhua Zhou

Zhi-Qiang Niu

Albert M Wu

Xiaoguang Zeng

Mary Jane R Alin

Sehat Sutardja

Lingpeng Guan

Xiaobin Wang

Shih-Ked Lee

Jeong Yeol Choi

Poh Boon Leong

Wenjun Li

Lijuan Zhang

Lin Chen

Jian Yin

Hongyong Xue

Peter L Wilson

Scott Wu

Guo-Qiang (Patrick) Lo

Marc Jacobs

Feng Ye

Ohm-Guo Pan

Guobing Shen

Ronen Sinai

Lin Lv

Chen Lung Tsai

Tze-Pin Lin

Zhen Du

Lei Fukuda

David Brian Oraboni, Jr

Adrian Chee Heong Koh

Yingbo Jia

Hailin Zhou

A semiconductor package includes a lead frame, a chip, and a molding encapsulation. The lead frame comprises a die paddle, a first plurality of leads, additional one or more leads, a second plurality of leads, a first tie bar, a second tie bar, a third tie bar, and a fourth tie bar. A respective end surface of each lead of the first plurality of leads, the additional one or more leads, and the second plurality of leads is plated with a metal. A respective end surface of the first tie bar, the second tie bar, the third tie bar, and the fourth tie bar is not plated with the metal. A method for fabricating a semiconductor package includes the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, applying a trimming process, applying a plating process, and applying a singulation process.

Semiconductor package having wettable lead flanks and tie bars and method of making the same

A semiconductor device comprises a semiconductor substrate, a plurality of metal layers, an adhesive layer, a compound layer, and a plurality of contact pads. A thickness of the semiconductor substrate is in a range from 15 μm to 35 μm. A thickness of the compound layer is larger than the thickness of the semiconductor substrate. A coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C. A glass transition temperature of the compound layer is larger than 150° C. The plurality of metal layers comprises a first titanium layer, a first nickel layer, a silver layer, a second nickel layer, and a metallic layer. In a first example, the metallic layer is a second titanium layer. In a second example, the metallic layer is a Titanium Nitride (TiN) layer.

Chip scale package (CSP) semiconductor device having thin substrate

A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.

Semiconductor package having mold locking feature

A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.

Semiconductor package having thin substrate and method of making the same

A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.

Wafer level chip scale semiconductor package

A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.

DMOS FET chip scale package and method of making the same

A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles, a first plurality of leads, and a second plurality of leads. A respective end surface of each lead of the first plurality of leads and the second plurality of leads is plated with a metal. A first respective window on a first side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A second respective window on a second side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A method for fabricating a semiconductor package comprises the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, and applying a cutting process or a punching process.

Semiconductor package having wettable lead flank and method of making the same

A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulation process so as to form a plurality of semiconductor packages.

A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.

Method for semi-wafer level packaging

A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.

Power semiconductor package having integrated inductor, resistor and capacitor

A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.

Super-fast transient response (STR) AC/DC converter for high power density charging application

A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.

Semiconductor package having enlarged gate pad and method of making the same

A process is applied to develop a plurality of reverse conducting insulated gate bipolar transistors (RCIGBTs). The process comprises the steps of providing a wafer, applying a first grinding process, patterning a mask, applying an etching process, removing the mask, implanting N++ type dopant, applying a second grinding process forming a TAIKO ring, implanting P+ type dopant, annealing and depositing TiNiAg or TiNiVAg, removing the TAIKO ring, attaching a tape, and applying a singulation process. The mask can be a soft mask or a hard mask. The etching process can be a wet etching only; a wet etching followed by a dry etching; or a dry etching only.

Method of making reverse conducting insulated gate bipolar transistor

A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.

Semiconductor package and method of making the same

A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a 'drain 1, drain 2, drain 1, and drain 2' pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.

Common source land grid array package

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Cupertino, CA, United States of America

Long-Ching Wang