Cambridge Gan Devices Limited

Cambridge Enterprise Limited

Siliconix Incorporated

Loizos Efthymiou

Florin Udrea

Giorgia Longobardi

Martin Arnold

John William Findlay

Sheung Wai Fung

Gianluca Camuso

David Bruce Vail

Tara Vishin

Philip Neaves

Max Shih-kuan Chen

Hao-Che Chien

A III-nitride power semiconductor based heterojunction device comprising a substrate, a first terminal, a second terminal, a control terminal configured to receive an input switching signal during an active mode of operation and to not receive the input switching signal during a stand-by mode of operation, and an active heterojunction transistor formed on the substrate. The device further comprises a stand-by signal generation circuit configured to generate a stand-by signal when the input switching signal to the control terminal has not been detected for a set period of time, at least one Miller clamp transistor and driving circuitry associated with the at least one Miller clamp transistor, a voltage regulator circuit configured to provide at least a low power consumption output and a high power consumption output, wherein the low power consumption output is enabled at least during the stand-by mode of operation and the high power consumption output is disabled by the stand-by signal during the stand-by mode of operation, and a rail voltage terminal configured to provide an input to the voltage regulator circuit. The low power consumption output is provided to the driving circuitry of the at least one Miller clamp transistor to thereby maintain the at least one Miller clamp transistor in an on-state during the stand-by mode of operation, and the low power consumption output is provided to the stand-by signal generation circuit to thereby power up the stand-by signal generation circuit.

Stand-by circuit

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

Power semiconductor device with an auxiliary gate structure

We describe a heterojunction based half bridge apparatus formed within a single active area comprising a first heterojunction device and a second heterojunction device, each heterojunction device comprising a drain and a source, each drain comprising a drain contact and each source comprising a source contact; wherein the drain contact of the first heterojunction device and the source contact of the second heterojunction device comprise a common contact. The half bridge apparatus according to the present disclosure may be advantageously more compact and more reliable than existing heterojunction based half bridges.

Heterojunction based half bridge

A power integrated circuit comprising: a heterojunction structure Gallium Nitride, GaN, chip comprising at least one GaN layer and at least one Aluminium Gallium Nitride, AlGaN, layer wherein the GaN chip comprises at least one main power device comprising a source terminal, a drain terminal, a gate terminal and a two-dimensional electron gas, 2DEG, formed at an interface between the AlGaN and GaN layers and between the source and drain terminals, wherein the gate terminal is configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal, a driver comprising at least one low-side component and at least one high-side component, wherein the low-side component comprises a terminal connected to a low DC voltage rail and at least one other terminal connected to the gate terminal of the main power device; wherein the high-side component comprises at least one terminal connected to a high DC voltage rail and at least one other terminal connected to the gate of the main power device; wherein the at least one low-side component of the driver is configured to discharge an input capacitance of the main power device during a turn-off of the main power device and is monolithically integrated within the GaN chip; and wherein the at least one high-side component of the driver is configured to charge up the input capacitance of the main power device and is formed in a semiconductor region comprising a material other than GaN.

Mixed material power devices and driver circuits

An Ill-nitride semiconductor based heterojunction power device is disclosed and includes a first and second heterojunction transistors formed on a substrate. The first and second heterojunction transistors include first and second Ill-nitride semiconductor regions formed over the substrate. The first Ill-nitride semiconductor region includes a first heterojunction, a first terminal connected to the first Ill-nitride semiconductor region, a second terminal laterally spaced from the first terminal and connected to the first Ill-nitride semiconductor region, and a first gate region over the first Ill-nitride semiconductor region between the first and second terminals. The second Ill-nitride semiconductor region includes a second heterojunction, a third terminal connected to the second Ill-nitride semiconductor region, a fourth terminal laterally spaced from the third terminal and connected to the second Ill-nitride semiconductor region, first highly doped semiconductor regions of a first conductivity type formed over the second Ill-nitride semiconductor region.

III-V semiconductor device with integrated power transistor and start-up circuit

We disclose a Ill-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor () formed on a substrate, the first heterojunction transistor comprising: a first Ill-nitride semiconductor region formed over the substrate, wherein the first Ill-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal () operatively connected to the first Ill-nitride semiconductor region; a second terminal () laterally spaced from the first terminal and operatively connected to the first Ill-nitride semiconductor region; a first gate terminal () formed over the first Ill-nitride semiconductor region between the first terminal and the second terminal. The device also includes a second heterojunction transistor () formed on a substrate, the second heterojunction transistor comprising: a second Ill-nitride semiconductor region formed over the substrate, wherein the second Ill-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a third terminal operatively connected to the second Ill-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second Ill-nitride semiconductor region, wherein the fourth terminal is operatively connected to the first gate terminal; and a second gate terminal formed over the second Ill-nitride semiconductor region between the third terminal and the fourth terminal and wherein the second heterojunction transistor is used in sensing and protection functions of the first power heterojunction transistor. The device also includes at least one monolithically integrated current sensing transistor () that has a substantially identical structure to the first heterojunction transistor, and wherein the third transistor is scaled to a smaller area or a shorter gate width when compared to the first heterojunction transistor by a scale factor, X, where X is larger than 1. Other embodiments include both internal and external sensing, sensing loads and a feedback circuit to provide overcurrent, gate over-voltage or over-temperature protection.

III-V semiconductor device with integrated protection functions

We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. A pull-down network for the switching-off of the high threshold voltage GaN transistor may be formed by additional auxiliary low-voltage GaN transistors and resistive elements connected with the low-voltage auxiliary GaN transistor.

An integrated circuit is provided which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.

III-nitride power semiconductor based heterojunction device

The present disclosure relates to an edge detection circuit configured to receive an input signal comprising one or more falling or falling edges and provide an output signal comprising pulses or spikes corresponding to the one or more rising or falling edges. The edge detection circuit comprises a passive differentiator circuit configured to receive an input and provide a differentiator output signal that that is proportional to the rate of change of the input, and a comparator circuit operably connected to a voltage source. The comparator circuit is configured to receive the differentiator output signal, compare the differentiator output signal to a threshold voltage; and output a pulse or spike signal based on the comparison to the threshold voltage.

Edge detection circuit

A III-nitride semiconductor based heterojunction power device including: a first heterojunction transistor formed on a substrate, and a second heterojunction transistor formed on the substrate. One of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor. The enhancement mode transistor acts as a main power switch, and the depletion mode transistor acts as a start-up component.

The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. In other embodiments a pull-down network for the switching-off of the high threshold voltage GaN transistor is formed by additional auxiliary low-voltage GaN transistors and resistive elements connected in parallel or in series with the low-voltage auxiliary GaN transistor.

A device includes a heterojunction device, a unipolar power transistor operatively connected in series with said hetero junction device; an external control terminal for driving said unipolar power transistor and said heterojunction device; and an interface unit having a plurality of interface terminals. A first interface terminal is operatively connected to an active gate region of the heterojunction device and a second interface terminal is operatively connected to said external control terminal. The heterojunction device includes a threshold voltage less than a threshold voltage of the unipolar power transistor, wherein the threshold voltage of the heterojunction device is less than a blocking voltage of the unipolar power transistor.

Power semiconductor device with a series connection of two devices

The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.

The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary gate terminal () and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device () and a low-voltage auxiliary GaN device () wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. In other embodiments a pull-down network for the switching-off of the high threshold voltage GaN transistor is formed by a diode, a resistor, or a parallel connection of both connected in parallel with the low-voltage auxiliary GaN transistor.

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Cambridge, United Kingdom

Loizos Efthymiou