Nxp Usa, Inc.

Institut National Polytechnique De Toulouse (inpt)

Institut National Polytechnique De Toulouse

Loic Hureau

Thomas Henry Luedeke

Jean-Philippe Meunier

Daniel McKenna

Ray Charles Marshall

Alaa Eldin Y El Sherif

Maxime Clairet

Marc Michel Cousineau

Mohit Satsangi

Daniel Mckenna

Jean-Phlippe Meunier

Monitoring for an over-voltage condition based on a regulated voltage is disclosed. A first terminal of a voltage regulator receives a first voltage which is based on a regulated voltage input to a controller. A second terminal of the voltage regulator receives a second voltage indicative of the voltage input to the controller. A determination is made whether the first voltage exceeds the first voltage reference for a first time window and the controller is reset based on the determination that the first voltage exceeds the first voltage reference. A determination is also made whether the second voltage exceeds the second voltage reference for the second time window and the voltage regulator is powered down on based on the determination that the second voltage exceeds the second voltage reference.

Voltage regulator which redundantly monitors for an over-voltage condition based on a regulated voltage provided to a controller and methods

Power management circuitry includes a power management circuitry having a handshake watchdog (HWD) timer and configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at a first input and a qualified wakeup request expected at a second input and configured to start the HWD timer counting in response to the initial wakeup request. Processing circuitry includes a wakeup signal aggregator configured to receive wakeup signals from internal and external wakeup events and to provide a notification of an occurrence of a wakeup event. The notification is provided as the initial wakeup request. A low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and to provide the qualified wakeup request as a result of performing at least a portion of the exit sequence.

Processing wakeup requests in a processing system having power management circuitry and a processing circuitry

A cascaded power system including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled and otherwise discharges the core voltage. The comparator circuitry monitors the voltage levels of the supply and core voltages and the control circuitry performs handshaking with the slave circuitry based partly on the voltages to ensure smooth transitioning between the normal and low power modes. The control circuitry asserts a low power good signal when the supply and core voltages are discharged, and de-asserts the low power good signal when the supply and core voltages are fully charged. A processor may rely on the low power mode signal for transitioning between power modes.

Power mode transition management for cascaded power supply

A local control-unit operable as a master or a slave comprises: a memory indicative of whether the converter sub-unit is enabled or disabled; and an enable; a wake-up output; a communication link input and output interfaces configured to receive and to send master/slave information; and a further communication link input and output interfaces, configured to both enable current balancing and phase interleaving with other enabled converter sub-units; and being adapted and configured to: in response to the respective local output current being higher than a first threshold, send a wake-up request to the next converter sub-unit; and in response to (a) being a slave sub-unit; (b) the respective local output current being lower than a second threshold, and (c) receiving master/slave information indicative that the next enabled sub-unit is a master sub-unit, disabling itself. Methods of operating the same are also disclosed.

Multiphase DC to DC converters with phase shedding, and sub-units and methods therefor

A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.

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Toulouse, France

Loic Hureau