Hughes Aircraft Company

Hughes Electronics Corporation

Loi D Nguyen

Minh V Le

Michael J Delaney

Umesh Kumar Mishra

Mehran Matloubian

Lawrence E Larson

Adele E Schmitz

William E Stanchina

Robert A Metzger

Mark Lui

April S Brown

Linda M Jelloian

Joseph A Henige

Jeff B Shealy

James C Loh

Jorge L Tizol

A structure and method for making HEMTs with a gate metal having a layer comprising titanium, a layer comprising vanadium over the layer comprising titanium, and a layer comprising gold over the layer comprising vanadium. Such HEMTs are insensitive to hydrogen.

Structure and method for making FETs and HEMTs insensitive to hydrogen

A metal system that can be adjusted to obtain higher alloying temperatures in AlInAs/GaInAs heterostuctures is disclosed. Increasing the thickness of a Ag layer in the metal system facilitates higher alloying temperatures and, consequently, improved ohmic contact reliability. The system is particularly directed to use in Al.sub.x In.sub.1-x As/Ga.sub.0.47 In.sub.0.53 As with 0.48&lt;x&lt;1 power HFETs.

Fabrication process for Al.sub.x In.sub.1-x As/Ga.sub.y In.sub.1-y As

A method for hydrogen treatment of FETs for use in hermetically sealed packages is disclosed. FETs such as GaInAs HEMTs are treated before hermetic packaging by heating them in a hydrogen atmosphere until their drain currents degrade, and then continuing to heat them until their drain currents are restored. The HEMTs' drain currents are monitored and the process is continued until the currents stabilize. Thereafter the devices' temperature is lowered to the desired operating temperature and their drain currents are measured. If the drain currents after treatment are close enough to the current levels before treatment, the devices are selected; otherwise they are rejected.

Method for hydrogen treatment of field effect transistors for use in

Yields of FETs such as HEMTs are significantly improved by establishing an elongate gate contact opening in a patterning material with the patterning material overhanging the opening along both its elongate sides and its ends. A contact metal is next evaporated both into the opening and onto the adjacent patterning material, with the overhang producing a continuous gap around the periphery of the upper section of the gate contact between it and the metal on the adjacent patterning material. The adjacent metal is then lifted-off without disturbing the gate contact. The inward tapered profile in the elongate direction of the contact opening is achieved with multiple parallel e-beam scans, while a similar profile is achieved at the ends of the elongate scans by increasing the electron beam dose in the vicinity of the scan ends, preferably by scanning the beam at a substantial angle to the elongate direction near the ends of the opening.

High yield sub-micron gate FETs

Yields of FETs such as HEMTs are significantly improved by establishing an elongate gate contact opening in a patterning material with the patterning material over-hanging the opening along both its elongate sides and its ends. A contact metal is next evaporated both into the opening and onto the adjacent patterning material, with the overhang producing a continuous gap around the periphery of the gate contact between it and the metal on the adjacent patterning material. The adjacent metal is then lifted-off without disturbing the gate contact. The inward tapered profile in the elongate direction of the contact opening is achieved with multiple parallel e-beam scans, while a similar profile is achieved at the ends of the elongate scans by increasing the electron beam dose in the vicinity of the scan ends, preferably by scanning the beam at a substantial angle to the elongate direction near the ends of the opening.

High yield electron-beam gate fabrication method for sub-micron gate FETS

A donor layer (17) including an undoped wide bandgap material (14) and an n-type dopant (16) is deposited on a substrate (12) by molecular beam epitaxy (MBE) at a first temperature which is high enough for optimal growth of the donor layer (17). The dopant (16) is silicon or another material which exhibits surface segregation in the wide bandgap material (14) at the first temperature. An undoped spacer layer (18) of the wide bandgap material is deposited on the donor layer (17) at a second temperature which is sufficiently lower than the first temperature that surface segregation of the dopant material from the donor layer (17) into the spacer layer (18) is substantially suppressed. A channel layer (20) of a narrow bandgap material is formed on the spacer layer (18) at a third temperature which is higher than the second temperature and selected for optimal growth of the channel layer (20). The spacer layer (18) is substantially undoped, and the low temperature growth and reduction of donor movement reduces ionized impurity scattering in the channel layer (20).

Method of fabricating inverted modulation-doped heterostructure

A channel layer, donor layer, Schottky layer, and cap layer are formed on a substrate. A source and drain are formed on the cap layer. A gate is formed on the cap layer, or at the bottom of a recess which is formed through the cap layer and partially extends into the Schottky layer. The donor and Schottky layers are formed of a semiconductive material which includes an oxidizable component such as aluminum. A passivation or stop layer of a lattice-matched, non-oxidizable material is formed underlying the source, drain, and gate, and sealingly overlying the donor layer. The stop layer may be formed between the Schottky layer and the donor layer, or constitute a superlattice in combination with the Schottky layer consisting of alternating stop and Schottky sublayers. Alternatively, the stop layer may sealingly overlie the Schottky layer, and further constitute the cap layer.

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Thousand Oaks, CA, United States of America

Loi D Nguyen