Sandisk Corporation

Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Loc Tu

Charles Moana Hook

Yan Li

Jian Feng Chen

Liang Li

Nyi Nyi Thein

Kirubakaran Periyannan

Dat Tran

Jeffrey W Lutze

Jiahui Yuan

Jun Wan

Jian Chen

Tien-Chien Kuo

Long C Pham

Alex Mak

James Floyd Cardosa

Ian Arthur Myers

Yinfeng Yu

Sridhar Yadala

Xuan Tian

Qianqian Yu

Sowjanya Sunkavelli

Wangang Tsai

Sowjanya Tungala

Sini Balakrishnan

A non-volatile memory system reduces the number of bits of data per non-volatile memory cell for a block (or other grouping of non-volatile memory cells) in response to a failed memory operation, the block being subjected to more than a minimum number of programming cycles or other events. The reducing of the number of bits of data stored in the memory cells allows the useful life of the block to be extended.

Non-volatile memory that dynamically reduces the number of bits of data stored per memory cell

A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.

Non-volatile memory integrated with artificial intelligence system for preemptive block management

Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.

Obtaining threshold voltage measurements for memory cells based on a user read mode

A non-volatile storage apparatus comprises one or more memory die assemblies, each of which includes an inference circuit positioned in the memory die assembly. The inference circuit is configured to use a pre-trained model (received pre-trained from a source external to the non-volatile storage apparatus and stored in a dedicated block in non-volatile memory) with one or more metrics describing current operation of the non-volatile storage apparatus in order to predict a defect in the non-volatile storage apparatus and perform a countermeasure to preserve host data prior to a non-recoverable failure in the non-volatile storage apparatus due to the defect.

Non-volatile memory with pre-trained model and inference circuit

Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.

Circuit for detecting pin-to-pin leaks of an integrated circuit package

Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X&#x3e;1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.

Mapping consecutive logical block addresses to consecutive good blocks in memory device

A memory management method includes identifying memory segments of a memory device. The method also includes identifying, for each memory segment, a number of faulty columns and determining a total number of faulty columns for the memory device. The method also includes, in response to a determination that the total number of faulty columns is greater than a threshold, identifying a memory segment having a highest number of faulty columns. The method also includes disabling the memory segment. Another method includes identifying, for each memory segment, a number of faulty memory blocks and determining a total number of faulty memory blocks. The method also includes, in response to a determination that the total number of faulty memory blocks is greater than a threshold, identifying a memory segment having a highest number of faulty memory blocks. The method also includes disabling the memory segment.

Systems and methods for capacity management of a memory system

A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).

Memory card test interface

Techniques are disclosed herein for automatically self-disabling a memory die in the event that a programmable element on the memory die for indicating whether the memory die is defective cannot be trusted. Memory die are provided with chip enable circuitry to allow particular memory die to be disabled. If the programmable element can be trusted, the state of the programmable element is provided to the chip enable circuitry to enable/disable the memory die based on the state. However, if the programmable element cannot be trusted, then the chip enable circuitry may automatically disable the memory die. This provides a greater yield for multi-chip memory packages because packages having memory die with a programmable element that cannot be trusted can still be used.

Memory die self-disable if programmable element is not trusted

In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be used to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.

Non-volatile memory with linear estimation of initial programming voltage

Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be readdressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

Programmable chip enable and chip address in semiconductor memory

High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.

Method for non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage

High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.

Non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage

In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.

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San Jose, CA, United States of America

Loc Tu