Silicon Storage Technology, Inc.

Winbond Electronics Corporation

Winbond Memory Laboratory

Other

Winbond Electronics Corporation America

National Semiconductor Corporation

Windbond Electronics Corp.

Loc Bao Hoang

Hung Quoc Nguyen

Hieu Van Tran

Sang Thanh Nguyen

Anh Ly

Vishal Sarin

Thuan Vu

Sheng-Hsiung Hsueh

Steve Choi

Nasrin Jaffari

Wingfu AAron Lau

Dah-Bin Kao

Tung-Yi Chan

William Saiki

Isao Nojima

Albert T Wu

Albert M Wu

Alexander Kotov

Tam Minh Nguyen

Albert V Kordesch

Hung O Nguyen

Chun-Mail Liu

Ganshu Ben Lee

Jitendra R Kulkarni

Khoi V Dinh

A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

Fast start charge pump for voltage regulators

Fast voltage regulators for charge pumps

A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Flash memory array system including a top gate memory cell

A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

Test circuit and method for multilevel cell flash memory

Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreover, the top gate line may be dynamically coupled to the word line. Other exemplary implementations may relate to drivers for driving the word line and/or top gate line, multilevel memory cell, and/or floating gate line features.

Flash memory array with a top gate line dynamically coupled to a word line

Flash memory array having control/decode circuitry for disabling top gates of defective memory cells

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San Jose, CA, United States of America

Loc Bao Hoang