Packard Bell Nec

Zenith Data Systems Corporation

Advanced Micro Devices Corporation

Nec Corporation

Lloyd W Gauthier

Robert A Kohtz

David J DeLisle

Saifuddin T Fakhruddin

Mark D Nicol

David T DeRoo

Michael P Krau

Gary Michael Godfrey

Richard G Russell

Richard D Ball

Jimmy D Smith

Saifee Fakhruddin

Carl Kittredge Wakeland

David Francis Tobias

Mark J Foster

David J Delisle

Mark Tracy Ellis

Donald G Craycraft

Jim Mergard

Brian C Barnes

David R Veit

Faheem Hayat

The scalable virtual timer system or subsystem implements multiple hardware timers with minimal silicon overhead. In one embodiment, for each virtual timer of a plurality of virtual timers, a content addressable memory stores a sum of an &ldquo;initial state&rdquo; of a free running counter and a desired count duration for the virtual timer. When the stored value matches a current state of the free running counter, the content addressable memory generates a terminal count for the virtual timer. In an alternative embodiment, for each virtual timer, a period register of a set of period registers stores a sum of a desired count duration for a virtual timer and an &ldquo;initial state&rdquo; of the free running counter. A comparator of a set of comparators generates a terminal count for a virtual timer when a current state of the free running counter matches the sum stored in a period register associated with the virtual timer. A state of the free running counter may be read through software, such as by an execution unit, or through hardware, such as by an adder.

Scalable virtual timer architecture for efficiently implementing multiple hardware timers with minimal silicon overhead

A system provides pseudo-concurrency for a volatile memory and a non-volatile memory on a same data bus. In one system embodiment, the volatile memory is coupled to its own address bus, and the non-volatile memory is coupled to its own address bus. In another system embodiment, the volatile memory and non-volatile memory are coupled to a multiplexed address bus. Concurrent with an access cycle to the volatile memory, the non-volatile memory may be precharged. After the access cycle to the volatile memory, a data cycle to a non-volatile memory may be executed. Concurrent with an access cycle to the non-volatile memory, the volatile memory may be precharged. After the access cycle to the non-volatile memory, a data cycle to the volatile memory may be executed.

Pseudo-concurrency between a volatile memory and a non-volatile memory on a same data bus

A microcontroller is presented having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface. The microcontroller includes a central processing unit (CPU), a first set of I/O pads, and a configurable logic block (CLB) all formed upon a single monolithic semiconductor substrate. The CPU is configured to execute instructions, preferably x86 instructions. The CPU produces CPU output signals during instruction execution. The CLB is coupled between the CPU output signals and the first set of I/O pads, and is configurable to perform a logic function selected from a predefined set of logic functions. Each member of the set of logic functions has an associated hardware interface including a signal table which defines a correspondence between CLB input/output signals and members of the first set of I/O pads. The microcontroller also preferably includes a test/program core coupled to a second set of I/O pads and to the CLB. The test/program core produces programming signals in response to signals received via the second set of I/O pads. The programming signals cause the CLB to perform the selected logic function. When programmed, the CLB produces CLB output signals in response to the CPU output signals. Each of the CLB output signals is coupled to one or more of the members of the first set of I/O pads according to the hardware interface of the selected logic function.

Microcontroller having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface

A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are controlled by an arbitration circuit which allows one CPU to always have the highest priority. The primary CPU may or may not be the highest priority CPU in the arbitration scheme. The arbitration circuit is combined with a controlling mechanism which interfaces to the memory device. This controller operates at a clock rate fast enough to allow the highest priority CPU to access the memory at it's highest data rate and, yet, guarantees a maximum idle period for the lower priority CPU to wait for it's interleaved memory access to complete. A single memory device provides cost and space savings. A controller is responsive to these processors to multiplex their information signals for selectively conveying information present at their address and data ports. A common memory device is addressable by the processors, and responsive to the controller to share addressing of the common memory device.

Multiprocessor system for enabling shared access to a memory

An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.

Protected address range in an electrically erasable programmable read

A computer system employs a process on warm boot which obviates the need to copy code in non-volatile memory to volatile memory; a normal function in a warm boot process. The computer system checks a warm boot flag which indicates that the code was previously copied on cold boot. By avoiding copying this already copied code and executing directly from the volatile memory considerable time is saved. Since BIOS code is typically on the order of 10K bytes, elimination of the necessity to rewrite BIOS and vectoring directly to BIOS image file in RAM saves on the order of ten thousand clock cycles.

Method for warm boot from reset

In the present invention, a single EEPROM is used to store firmware for the CPU, firmware for the SCP and the system password and other critical system data. Hardware protection is provided that prevents the CPU from accessing the portion of the EEPROM that contains the password or other critical systems data.

Method to store privileged data within the primary CPU memory space

The invention provides for a CPU in a digital system to control the location of the code being executed by one or more peripheral CPUs when all CPUs share a common memory. This allows the CPU to allocate convenient (e.g., unused) blocks of its address space for the code for the peripheral CPU(s). Additionally, for digital systems in which the peripheral CPU(s) cannot address the full range of the address space of the shared memory that is available to the CPU, the CPU can control the relocation of the block of code for the peripheral CPU(s) (i.e., provide a code paging system).

Apparatus to allow a CPU to control the relocation of code blocks for

The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are possible, but only under controlled conditions. Once the register has been programmed, it will no longer respond to writes.

Write inhibited registers

A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

Hardware based interface for emulation of a standard system control

An apparatus and method for tracking and interception of instructions as they are presented to the memory, selectively passing harmless data to the device and disallowing the sequences which instruct the device to perform harmful functions, such as self-erase. A software trap is provided to be transparent to the operation of the device and the host system, imposing no harmful timing delays or software overhead. Accordingly, the invention allows the use of standard electrically erasable read-only memories in an application which requires that the device be protected from global erasure. A hardware front end intercepts the software command which is used to globally erase the device. The apparatus receives address signals from the computer system corresponding to the protected peripheral device, receives data signals from the computer system to the protected peripheral device, tracks a predetermined sequence of address and address signals, substitutes at least one of the data signals received with a replacement data signal, and sends a replacement data signal.

Method to prevent data loss in an electrically erasable read only memory

Hardware based interface for mode switching to access memory above one

A plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor. One processor is dedicated to at least one peripheral device. Since the system control processor is not burdened with the relatively slow communications protocol with the peripheral devices, it is free to do other tasks which improves the overall system performance. Communication protocol between the dedicated processors allows for local and global communication.

Personal computer having dedicated processors for peripheral devices

A personal portable computer having a fluorescent backlit LCD is provided with circuitry for mitigating noticeable flicker of the backlight. The signal driving the backlight is synchronized with the display refresh signal. More particularly, a horizontal sync signal from an LCD driver is applied to a counter which divides the horizontal sync signal by a predetermined amount. The counter is reset after each frame of the display is written by a vertical sync signal. The output of the counter is applied to a pluse width modulator, such as a monostable multivibrator, which provides a signal to the backlight, synchronized with the display refresh signal. The circuitry also allows for the duty cycle of the backlight signal to be adjusted to control the brightness of the display and consequently the power drain on the battery.

Growing community of inventors

Austin, TX, United States of America

Lloyd W Gauthier