Unisys Corporation

Lloyd E Thorsbakken

Larry L Byers

Michael R Overley

Wayne A Michaelson

Gary R Robeck

Joseba M Desubijana

Joseba M De Subijana

Michael E Mayer

Steven M Wierdsma

Jerome G Carlin

Howard Huy Tran

Randall L Piper

Donald M Davies

A system and method for providing a desired degree of fairness of access to data transfer resources by a plurality of command-initiating bus agents. A bus arbiter allocates general ownership of the bus to one of a plurality of bus agents, and a fairness module imposes a desired degree of fairness to the data transfer resources by mandating data transfer resource access to bus agents whose commands have been subjected to a retry response. The degree of fairness is controllable, in order to appropriately balance the desired throughput and data transfer resource allocation for a particular application.

System and method for managing input/output requests using a fairness throttle

A method of and apparatus for improving the efficiency of a data processing system employing multiple busses operating at multiple data transfer rates. Each of the multiple physical busses has its own characteristics including maximum data transfer rate, parallel word width, etc. Two or more of these physical busses are combined into a single logical bus, wherein the single logical bus has characteristics resulting from the combination of physical busses. These characteristics can include greater parallel word widths, enhanced maximum data transfer rates, etc.

Logical PCI bus

An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage device includes a copy of the selected address. During a subsequent read operation, the copy of the address is read from memory and compared to the read address used to perform the memory access. If the addresses are not the same, a potential addressing fault occurred within the control logic of the storage device. The fault detection system is particularly adaptable for use with storage devices having a relatively small number of addressable locations, each containing a relatively large number of bits. According to one embodiment of the invention, the storage device is a General Register Array (GRA) utilized as a queue.

System and method for detecting faults in storage device addressing logic

A system for communicating data between a main processor and a peripheral processor over a fiber optic interface. The interface is a dedicated, point-to-point link operating in full-duplex, asynchronous mode. Dual fibers and physical layer controllers are used in a cascaded fashion to double the throughput of the interface. Frame control logic coordinates formatting of data into frames for transmission over the interface. Frame format and interface protocol are based on FDDI, but are improved to more efficiently transfer data in a point-to-point implementation. Frame Check Sequences are generated and verified to ensure error-free data transfers. Frame sending and frame receiving logic communicate with the main and peripheral processors, accepting data transfer requests and forwarding received data.

Dedicated point to point fiber optic interface

A bus architecture and associated circuitry for providing communication between processors and multiple gate arrays whereby the size of the data being transferred may be either full words of 32-bits or 36-bits per word, or half words of 16-bits or 18-bits per word. Parity generation logic operates on the data to be sent over the bus to generate a parity value from the correct data bits depending on the selected data word size. Parity checking logic operates on the data received from the bus to check the parity of the correct data bits depending on the selected data word size.

Growing community of inventors

Blaine, MN, United States of America

Lloyd E Thorsbakken