Motorola Corporation

Zilog, Inc.

Codex Corporation

Lloyd A Hasley

Paul M Anderson

Gyle Dee Yearsley

William James Tiffany

Joseph Keren-Zvi

Craig S Holt

Carol Jens

Chris Hall

A single shared processing path is used as contexts are switched during processing. Each unique context is processed using a corresponding unique pipeline. If a pipeline that is executing under one context stalls, processing is switched in the shared processing path to another pipeline that is executing under second context. New pipelines are enabled for execution by borrowing a clock cycle from the currently executing pipeline. In some cases contexts are assigned various relative priority levels. In one case a context switching microprocessor is used in a communication engine portion of a system-on-a-chip communication system.

Context switching pipelined microprocessor

Data processing system (800) and process (100) produce a hierarchical interconnection description of an integrated circuit design from a plurality of functional modules and a desired hierarchy. After an integrated circuit description is received (102), an interconnection structure is created (104) for each hierarchical level and functional module within the integrated circuit description. Based upon the desired hierarchy, a hierarchical tree is generated. Based upon the hierarchical tree, the interconnection structures are filled (106) with relevant interconnection and pin information to define interconnections among functional modules and hierarchical levels. After each interconnection structure is filled, a complete hierarchical interconnection description of the integrated circuit design has been completed. Finally, the hierarchical interconnection description is output (108). The present invention also includes generating a higher functional level description of an integrated circuit from a lower functional level description (300). Further included is a technique for generating integrated circuits based upon the present invention.

Method and apparatus for generating a hierarchical interconnection

A fiber data distributed interface (FDDI) system uses an MLT3A encoding scheme in order to reduce DC bias or baseline wander. The MLT3A encoding scheme is a scheme wherein logical zeros are transmitted as ground voltages and logical ones are transmitted as one of either positive voltages or negative voltages depending upon past transmission history (FIG. 4 ) wherein the past history is recorded by a counter C or an analog circuit. MLT3A ensures that the baseline wander or DC bias returns to zero or is maintained as close to zero as possible in a timely manner so that no FDDI systems will fail from baseline wander.

Apparatus and method for encoding data in a fiber data distributed

An integrated circuit for use in fiber distributed data interface (FDDI) system has four elastic layer and buffer management (ELM) circuits (12, 14, 16, and 18) coupled through a crossbar switch (20). The crossbar switch (20) allows any of the ELM circuits (12, 14, 16, and 18) to be coupled to any other ELM circuit (12, 14, 16, or 18) or to one of three external buses for FDDI communication. By using a crossbar switch and four ELM devices on a single integrated circuit, FDDI performance is improved while system design is made easier and more flexible than previously possible. Cipher circuitry (22, 24, 26, and 28) is used to scramble and descramble data ingoing and outcoming from the ELM devices. Concentrators, workstations, local area networks (LANs), and the like may incorporate the circuit (10) to improve performance and flexibility.

Method for switching data flow in a fiber distributed interface (FDDI)

An integrated circuit for use in fiber data distributed interface (FDDI) system has four elastic layer and buffer management (ELM) circuits (12, 14, 16, and 18) coupled through a crossbar switch (20). The crossbar switch (20) allows any of the ELM circuits (12, 14, 16, and 18) to be coupled to any other ELM circuit (12, 14, 16, or 18) or to one of three external buses for FDDI communication. By using a crossbar switch and four ELM devices on a single integrated circuit, FDDI performance is improved while system design is made easier and more flexible than previously possible. Cipher circuitry (22, 24, 26, and 28) is used to scramble and descramble data ingoing and outcoming from the ELM devices. Concentrators, workstations, local area networks (LANs), and the like may incorporate the circuit (10) to improve performance and flexibility.

Local area network data processing system containing a quad elastic

Arbitration is performed among a plurality of users for access to a shared resource in a system of the kind in which the users arbitrate by placing arbitration signals on a line and subsequently comparing their arbitration signals with a signal appearing on the line, by providing the users with independently operating clocks, and controlling the progression of the arbitration based on timing provided by the clock of at least one of the users. The progression of the arbitration thus does not depend upon a single master clock, or upon synchronizing the individual user clocks. Users that request access are assigned a first priority in the arbitration based at least on an access priority preassigned to the request for access and on whether the user is a member of a current group of users that is formed at a time during the arbitration when another group of users is empty, the current group including users that have been denied access as of that time; at least a portion of each user's arbitration signal is arranged as a multibit word having a value that represents the first priority, and each user that arbitrates for access places its multibit word in parallel on the path and determines whether it has won the arbitration by subsequently comparing its multibit word value with the value of a multibit word that appears on the path.

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Austin, TX, United States of America

Lloyd A Hasley