Honeywell Information Systems Inc.

Honeywell Bull, Inc.

Llewelyn S Dunwell

John L Curley

Richard A Lemay

William E Woods

Arthur Peters

Robert C Miller

Richard P Brown

Theodore R Staplin, Jr

Michael D Smith

A data processing system includes a logical address to a physical address translator in an extended memory management unit. A 128 word memory stores task segment descriptor words which include a base address. A 16 word memory stores corresponding present bits to indicate if the addressed task segment descriptor is present in its memory. This arrangement allows a 128 word memory to be cleared in 16 memory cycles.

Segment descriptor present bit recycle and detect logic for a memory

A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

Hardware demand fetch cycle system interface

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Lynn, MA, United States of America

Llewelyn S Dunwell