Syntest Technologies, Inc.

Lizhen Yu

Laung-Terng Wang

Shianling Wu

Zhigang Jiang

Hao-Jan Chao

Fangfang Li

Feifei Zhao

Jianping Yan

Jinsong Liu

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N&#x3e;1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Multiple-capture DFT system to reduce peak capture power during self-test or scan test

A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXeach having N input signals (dto d) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXeach having k+1 input signals from k redundant blocks (Rto R) and one base block (N), capable of being connected to N output signals (q); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.

Apparatus for redundancy reconfiguration of faculty memories

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Shanghai, China

Lizhen Yu