Nortel Networks Corporation

Liviu Calin

Radu Avramescu

Yuejian Wu

A built-in self test (BIST) for a multi-port compact sRAM (CsRAM) uses a BIST controller which operates at the speed of the system, while the CsRAM is tested at the memory speed. The circuitry for testing allows multiple random accesses of the CsRAM per system clock cycle. In this way, timing-related defects in the CsRAM can be detected. The CsRAM is virtually partitioned into &ldquo;k&rdquo; sections, the sections being tested simultaneously from different ports with identical and complementary test data. A conventional (BIST) controller can be used with minimal addition of hardware in a collar arranged around the memory array.

At-speed built-in self testing of multi-port compact sRAMs

Modifications to CAM cell designs are required as supply voltages utilized decrease. In one possible modified design, when a reference bit applied to the CAM cell matches a stored bit, p-channel pass transistors within the CAM cell can pass a full logical high to an n-channel chain transistor coupled within a NAND configuration with other CAM cells. This full logical high can result in increased transition speed, a decrease in degradation, and/or a decrease in power dissipation for the n-channel chain transistor. Further, compared to using n-channel pass transistors, the use of p-channel pass transistors to transfer the logical high voltage can increase the transition speed, decrease the degradation, and/or decrease the power dissipation for the pass transistors. Alternatively, the use of n-channel pass transistors and a p-channel chain transistor can gain similar advantages if the logic was opposite.

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Ottawa, Canada

Liviu Calin