Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Micron Technology Incorporated

Sgs Microelettronica Spa

Sgsates Componenti Elettronici S.p.a.

Livio Baldi

Marcello Mariani

Federico Pio

Danilo Re

Paolo Giuseppe Cappelletti

Alfonso Maurelli

Cesare Clementi

Paolo Ghezzi

Emilio Giambattista Ghio

Maria Santina Marangon

Giuseppe Meroni

Alessia Pavan

Bruno Vajana

Pietro Erratico

Giuseppe Corda

Giorgio De Santi

Paola Paruzzi

Aldo Maggis

Giulio Iannuzzi

Franco Maggioni

Daniela Beardo

Adriana Rebora

Maurelli Alfonso

Marco Icardi

Alessandro Tonti

A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.

Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls

A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.

Method for manufacturing non-volatile memory cells on a semiconductor substrate

A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plurality of floating gate regions are defined by forming stripes of shielding material only above pairs of alternated active areas. Spacers of a selective material are defined with respect to the shielding material and of small width at will in the shelter of the side walls of the stripes thus defined. A shielding material is also deposited on the active areas which lacked it. The formation of the floating gate is completed by leaving the definition of the distance between the floating gate regions to the spacers.

Matrix of memory cells formed using a method allowing for a self-alignment of the respective source region with the respective field oxide layer and the respective overlying polysilicon layer of each single cell of the matrix, the matrix including at least one first ROM memory cell suitable for permanently storing a first logic level, associated with a respective row and a respective column of the matrix, the first cell including a silicon substrate of a first conductivity type over which a first isolation region and a second isolation region are formed delimiting therebetween a longitudinal stripe, a gate element extending transversally through the stripe from at least one side of the first isolation region to at least one side of the second isolation region, a third region of a second conductivity type and a fourth region of a second conductivity type formed in the substrate along the stripe, and a field oxide region adapted to prevent the formation of a conductive channel in the substrate, and at least a second ROM cell for permanently storing a second logic level, identical to the first ROM memory cell but not provided with the field oxide region.

Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process

A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell. Between selectively etching the dielectric and depositing a second polysilicon layer, a first sub-step of removing the first gate oxide layer in the region for the logic transistor, and a second sub-step of growing a second oxide gate layer over the region, the second gate oxide layer having a different thickness than the first gate oxide layer.

Method of manufacturing an integrated semiconductor device having a nonvolatile floating gate memory, and related integrated device

A currency note includes an identification and/or authentication element including an integrated circuit. The integrated circuit can store, securely in electronic form and accessible from outside, such information as: the value, serial number, issuer, and date of issuance.

Currency note comprising an integrated circuit

The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.

Method of fabricating flat fed screens, and flat screen obtained thereby

A method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers wherein, after a preliminary step of providing contact holes in a layer of dielectric material: a prebarrier layer of Ti or TiN is formed overall; a layer of tungsten is formed by chemical vapor deposition so as to coat the bases and the walls of the contact holes uniformly; aluminum or an alloy thereof is sputter-deposited, under high-temperature low-flux conditions, to fill the contact holes; and patterning the aluminum and tungsten layers to form metallic interconnections of predetermined geometry.

Method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers

A high voltage capacitor, integratable monolithically on a semiconductor substrate which accommodates a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer, comprises two elementary capacitors having a first common conductive plate which is formed in the first layer of polycrystalline silicon. Each of these elementary capacitors has a second conductive plate formed in the second layer of polycrystalline silicon above the first plate, and includes said interpoly dielectric layer as an isolation dielectric between the two plates.

High voltage capacitor

The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and lacking the second source diffusion.

P-channel memory cell and method for forming the same

Method of fabricating flat FED screens

Growing community of inventors

Agrate Brianza, Italy

Livio Baldi