Synopsys, Inc.

Lisa R McIlwain

In-Ho Moon

Guillermo R Maturana

Eyal Odiz

Fahim Rahim

Arturo Salz

John W Hagerman

Dipti Ranjan Senapati

Guillaume Plassan

Demosthenes Anastasakis

Michael S Quayle

Phillip W Baraona

Patrick Groeneveld

Slawomir Pilarski

Kshama Jambhekar

Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes performing a minimization of the edge function, and in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.

Formal gated clock conversion for field programmable gate array (FPGA) synthesis

Techniques and systems for concurrent formal verification of logic synthesis are described. A synthesis tool can write intermediate checkpoint designs that embody the state of an integrated circuit (IC) design under synthesis as optimization progresses. Meanwhile, formal equivalence checking proceeds in parallel with synthesis and checks the intermediate checkpoint designs for equivalence.

Concurrent formal verification of logic synthesis

Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification.

Reducing x-pessimism in gate-level simulation and verification

A method and apparatus for determining equivalence between two integrated circuit device designs. Functional blocks and compare points within a first design are compared with functional blocks and compare points in a second design to determine compare points that are matched. The integrated circuit designs are traversed net-wise and cut points are inserted at compare points that are matched and that are not determined to be constant. As each design is traversed, the design is flattened such that flat copies of both integrated circuit designs are obtained (that include the inserted cut points). The flat copies of the integrated circuit designs are then compared to determine equivalence.

Hierarchical verification for equivalence checking of designs

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Oregon City, OR, United States of America

Lisa R McIlwain