Intel Corporation

Lisa K Wu

Andrew Thomas Forsyth

Edward Thomas Grochowski

Dennis Ryan Bradford

Elmoustapha Ould-Ahmed-Vall

Robert Valentine

Bret L Toll

Milind Baburao Girkar

Robert Dale Cavin

Jonathan Cannon Hall

Suleyman Sair

Seth Abraham

Charles R Yount

Jesus Corbal San Adrian

Sridhar Samudrala

Jeffrey G Wiedemeier

James Charles Abel

Roger Espasa Sans

Santiago Galan Duran

Mark Jay Charney

Jesus Corbal

Thomas D Fletcher

George Zacharias Chrysos

Eric A Sprangle

Michael D Upton

Ramacharan Sundararaman

Mark Charney

Robert C Valentine

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Vector friendly instruction format and execution thereof

A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.

Super multiply add (super MADD) instructions with three scalar terms

An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.

Apparatus and method for efficient gather and scatter operations

Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.

Instruction and logic to provide vector linear interpolation functionality

A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor.

Prefetch with request for ownership without data

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San Francisco, CA, United States of America

Lisa K Wu