Seagate Technology Incorporated

Quantum Corporation

Lisa Fredrickson

Vladimir Kovner

LeRoy A Volz

Dennis C Stone

Clifford M Gold

Stanley M Chang

Dennis W Hogg

Peter Gillen

Michael Ou

Anuradha Sukhija

Reza M Dehmohseni

A method and apparatus for synchronizing a Viterbi detector to data frames corresponding to code words read from of a medium is provided. A timing pattern and a synchronization pattern is provided, the detector is synchronized to the synchronization pattern based upon the timing pattern, the detector is further synchronized to the data frame based upon the synchronization pattern

Frame synchronization for viterbi detector

A method and apparatus are provided for identifying errors in a detected sequence of values generates the detected sequence of values from channel samples using a detector designed for a channel with a first channel response characteristic. The detected sequence of values is filtered using a filter that emulates a second channel response characteristic to produce a sequence of simulated second channel samples. The channel samples provided to the detector are also provided to a second filter which emulates a response characteristic equal to the second channel response characteristic divided by the first channel response characteristic. This produces a sequence of actual second channel samples. A sequence of difference values is then generated by subtracting each of the simulated second channel samples from a corresponding actual second channel sample. Using the sequence of difference values, at least one error is identified in the detected sequence of values.

Method and apparatus for identifying errors in a detected sequence of values

An encoder is provided that converts data words into code words. The code words, when concatenated together, are such that sub-strings of consecutive first symbols in the code words have no more symbols than a maximum number; sub-strings having the maximum number of consecutive first symbols and beginning at selected locations within the code words appear without restriction, and sub-strings having the maximum number of consecutive first symbols and beginning at locations other than the selected locations appear only where the sub-string is concatenated with an acceptable secondary sub-string. A method is also provided for generating a set of such code words for an encoder.

Method and apparatus for generating code words with shifted tribit error protection

An encoder and a method of encoding successive data words into successive code words for transmission through a channel is provided. The encoder maps a first portion of each successive data word unchanged into a first portion of a corresponding one of the successive code words and maps a second portion of each successive data word into a second portion of a corresponding one of the code words according to a selected code. The successive code words are concatenated to form an encoded bit stream having a plurality of bit positions. The selected code imposes a run length constraint on the successive code words such that the encoded bit stream has a maximum possible run of ten consecutive binary zeroes in adjacent ones of the plurality of bit positions and imposes an interleave constraint on the selected code words such that the encoded bit stream has a maximum possible run of ten consecutive binary zeroes in every other one of the plurality of bit positions.

Encoder and a method of encoding for partial response channels

A phase detector for a timing control loop provided in a signal sampling system to control taking samples by a sampler of input signals provided to a signal sampling system to result in a signal sample sequence output using a slope estimator and an error determiner with a phase error estimator combiner. The combiner output is provided to a summer directly and through a delay element to form phase error estimates.

Phase detector estimator

Signals indicative of unencoded input data are encoded into a plurality of encoded sequences. A first subset of the plurality of encoded sequences are encoded according to a k constrained code of rate x/y and a second subset of the plurality of unencoded sequences are encoded according to a k constrained code of rate m/n wherein x/y&ne;m/n. The encoded sequences are transmitted to a partial response channel subject to noise. The encoded sequences are transmitted from the channel to a Viterbi detector having a trellis structure with a preselected, time-dependent pattern to create a time varying trellis structure for limiting a maximum length of parallel paths therethrough. The encoded sequences are detected with a Viterbi detector to provide detected, encoded sequences. The detected, encoded sequences are then decoded to provide an estimate of the input data.

High rate trellis code for partial response channels

In a peak detection system having a variable gain amplifier (VGA), a counter is initialized and a countdown is triggered. Each time a qualified peak is detected, the counter is re-initialized. If the countdown is completed, the VGA gain is updated. This method can be used to boost amplifier gain that is too low to generate a qualifying threshold, even while overlooking short periods of very low output.

Amplifier gain control method using conditional updating

A Viterbi PRML system and method providing a new code with distance properties such that some tribits are allowed but no longer sequences are allowed. A code rate 8/ 9 is constructed for EPR4 and E.sup.2 PR4 channels and the system independently maps 8-bit blocks of user data to 9-bit channel sequences. The precoder has transfer function, f(D)=1/(1.sym.D), and produces a binary channel input x(D), which is fed to a coder, to provide an output signal y(D), which is transmitted and corrupted by noise. The corrupted signal is received and fed to a Viterbi detector. The signal is decoded to produce an estimate of the 8-bit data bytes, as reconstructed to be freed from noise corruption. The encoding protocol of the invention is implemented in the encoder. The protocol is: no sequence of 4 consecutive transitions occurs in any 9-bit codeword; no 9-bit codeword ends with a sequence of 2 or more consecutive transitions; no 9-bit codeword begins with more than 2 consecutive transitions; and sequences of 3 consecutive transitions, if any, begin only on a 2nd, 4th, 6th, or 9th bit of said 9-bit codeword. The protocol is preferably augmented by an additional constraint: no 9-bit codeword has the same 1st, 3rd, 5th, 7th, and 9th bit. Other limitations on coding are described to enhance the performance of the system.

Signal error-correction system and method

Asymmetric channel data detection compensation

A digital peak detection system digitizes analog signals and provides absolute values to a series of one cycle delays, and to a sequence of comparator stages. Each digital sample is parallel compared to a number of preceding samples equal to the number of active comparator stages. Control signals activate comparator stages to determine sample comparison window length, including lengths exceeding the number of samples between recorded peaks. Peak detection is optimized using a variable gain amplifier whose gain is updated based upon amplitude difference between actual and desired peak samples. When sample amplitudes are smaller than a qualifier threshold, a countdown timer increases amplifier gain after lapse of a programmed time without detecting a qualified pulse. Gain is also updated when the analog to digital converter saturates. Initial gain values can be programmed, and gain stored at the end of a servo mode for future use in reducing gain control loop convergence time.

Method and apparatus for a digital peak detection system including a

Signal conditioning system for controlling data retrieval channel

According to the invention, a data integrity code including logical block address ('LBA') and circuit implementation are provided. The code and implementing circuitry are utilized to enable data block LBA verification during a block transfer and retrieval process. The preferred data integrity code has embedded LBA information and also serves as a crosscheck code used to detect miscorrection by an error correction code ('ECC'). In a preferred disk drive embodiment, data integrity block ('DIB') is provided to verify that the LBA value associated with a given data block in a host interface matches the value associated with that same data block in a buffer memory and in a data sequencer. In a preferred method of use, data integrity/cross-check redundancy with LBA is appended to data blocks transmitted to a buffer memory and verified after the data block has been transferred from the buffer. After verification, the LBA is preferably written to the storage medium together with its associated data block to enable later LBA verification for blocks recovered from the storage medium. The LBA may also be verified when the data block is transferred back to a host from the buffer memory.

Data integrity and cross-check code with logical block address

Matched spectral null encoder/decoder

A system architecture for implementing a 10-bit Reed-Solomon code for detecting and correcting data errors in a single code word to protect a data block containing up to 1023 10-bit data symbols, i.e., the equivalent of up to 1278 8-bit symbols, including error check redundancy, maximizes the use of all allocated error correction overhead for an entire block of data, regardless of the particular error pattern characteristics encountered in a given system application. The architecture is particularly well suited for digital data processing and/or storage systems encountering non-bursty, (i.e., substantially random), error patterns, such is characteristic of data storage and retrieval systems employing semiconductor based memory stores. 5-bit extension field operations, (i.e., over a Galois field GF(2.sup.5)), generated by using the irreducible polynomial, P.sub.32 (X)=X.sup.5 +X.sup.2 +1, over GF(2), are utilized to perform certain, requisite arithmetic functions over the Galois field GF(2.sup.10) with a hardware-minimized error correction architecture.

Dedicated ALU architecture for 10-bit Reed-Solomon error correction

A word-wise encoder circuit that processes word formatted data blocks in response to a word clock signal and generates redundancy in accordance with an 8 bit symbol code. The encoder is provided with two parallel data paths, each receiving one of the respective bytes halves of the received data words during one word clock period to implement an 8 bit symbol code in response to a word clock signal. The word-wise encoder replicates, in one word clock period, the state of the registers in a standard sequential encoder after two consecutive bytes have been processed in response to a byte clock. In a preferred embodiment, a word-wise encoder is used to implement a Reed-Solomon data integrity code. In this example, the word-wise encoder generates redundancy that is appended to associated data blocks temporarily stored in a block buffer memory within a data channel to provide a mechanism for detecting data errors caused by the buffer. A reduced hardware implementation of a word-wise encoder circuit is disclosed wherein a special choice of generator polynomial and Galois field representation allows a Galois field multiplier to be eliminated. In this embodiment, the encoder generates two bytes of redundancy per data block and the longest propagation path in the encoder traverses one multiplier and two adders.

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Ojai, CA, United States of America

Lisa Fredrickson