Sun Microsystems, Inc.

Lisa C Grenier

James H Ma

Michael Frank Deering

Ewa M Kubalska

Scott R Nelson

Yan Yan Tang

Elisa Rodrigues

Elena M Ing

Nimita Taneja

A graphics system comprising a scheduling network, a sample buffer and a plurality of filtering units. The sample buffer is configured to store sample generated by a rendering engine. The plurality of filtering units are coupled in a linear series. Each filtering unit of the linear series is configured to send a request for a scanline of sample bins to a first filtering unit of the linear series. The first filtering unit is configured to service the scanline requests by sending burst requests to a scheduling network and coordinating the flow of samples forming the bursts from the sample buffer to the filtering units.

Sample request mechanism for supplying a filtering engine

A crossbar switch is disclosed. The crossbar switch comprises a plurality of input sorting units and a plurality of merge and interleave units. Each input sorting unit is capable of receiving from a respective device an access request to any one of a plurality of physical memory devices. Each merge and interleave unit is capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device. Also disclosed is method implemented by the crossbar switch.

Self-optimizing crossbar switch

A system for managing the control of a bi-directional data bus between a master unit and a slave unit. The master couples to the slave through a request opcode bus, a reply opcode bus and the data bus. If the master is in a bus driving state (with respect to the data bus) and receives a read request, the master relinquishes bus control and sends a read request through the request opcode bus. The slave unit assumes bus control and sends the requested data through the data bus. If the master is in a bus sensing state and receives a write request, the master sends a last read opcode to the slave via the request opcode bus, and waits for the slave to return a special token through the reply opcode bus. Upon receiving the special token the master unit assumes bus control and performs the write transaction.

Opcode to turn around a bi-directional bus

A method and computer graphics system capable of implementing multiple pipelines for the parallel processing of graphics data. For certain data, a requirement may exist that the data be processed in order. The graphics system may use a set of tokens to reliably switch between ordered and unordered data modes. Furthermore, the graphics system may be capable of super-sampling and performing real-time convolution. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to receive graphics data and to generate a plurality of samples for each of a plurality of frames. The sample buffer, which is coupled to the graphics processor, may be configured to store the samples. The sample-to-pixel calculation unit is programmable to generate a plurality of output pixels by filtering the rendered samples using a filter.

Graphics system configured to parallel-process graphics data using multiple pipelines

A technique for arbitrating and selecting one access request to a shared memory from among multiple contenders is disclosed. In a first aspect, the invention includes a method for accessing a shared memory. The method includes receiving a plurality of access requests; presenting a plurality of characteristics for each access request; ascertaining a plurality of operational characteristics; and selecting one of the access requests for processing upon consideration of the access request characteristics and the operational characteristics. In a second aspect, the invention includes an arbitration and select logic (&ldquo;ASL&rdquo;) unit. The ASL unit comprises a plurality of input sorting units, each input sorting unit capable of receiving a respective access request and a merge and interleave unit (&ldquo;MIU&rdquo;). The MIU is capable of receiving a plurality of characteristics for each access request; receiving a plurality of operational characteristics; and selecting one of the access requests for processing upon consideration of the access request characteristics and the operational characteristics.

Growing community of inventors

San Jose, CA, United States of America

Lisa C Grenier