Mellanox Technologies, Ltd.

Mellanox Technologies Tlv Ltd.

Nvidia Corporation

Liron Mula

Gil Levy

Aviv Kfir

Barak Gafni

Dotan David Levi

Niv Aibester

Sagi Kuks

Zachy Haramaty

George Elias

Lion Levi

Ran Ravid

Elad Mentovich

Paraskevas Bakopoulos

Benny Koren

Ariel Almog

Avi Urman

Yuval Shpigelman

Eitan Zahavi

Yuval Itkin

Itamar Rabenstein

Eyal Srebro

Ran Sela

Ioannis (Giannis) Patronas

Lior Narkis

Matty Kadosh

Natan Manevich

Amiad Marelli

Oded Wertheim

Aviad Raveh

Aviad Levy

Guy Lederman

Roy Kriss

Oded Zemer

Alon Singer

Amit Kazimirsky

Shachar Bar Tikva

Eran Gil Beracha

Jacob Ruthstein

Dekel Dadon

Omer Sella

Noam Bloch

Idan Burstein

Roee Moyal

Avraham Ganor

Yaron Haviv

Ariel Shachar

Wojciech Wasko

Gal Yefet

Lavi Koch

Thomas Kernen

Alex Shpiner

Oren Duer

Bar Shapira

Omer Shabtai

Ofer Hayut

Chen Gaist

Jose Yallouz

Shridhar Rasal

Yonatan Piasetzky

David Mozes

Idan Matari

Ofir Merdler

Oren Tzvi Sela

Maty Golovaty

Shachar Dor

Michael Gandelman

Yoav Benros

Dimitris Syrivelis

Gal Shohet

Harold Rosenstock

Zvika Eyal

Amir Mizrahi

Miri Shtaif

Eduard Kvetny

Barry Spinney

Ziv Battat

Oren Matus

Michael Taher

Nir Getter

A device, communication system, and method are provided. In one example, a system for reducing latency in out-of-order data transfers is described that includes circuits to detect a network error; and in response to detecting the network error, transmit a notification to at least one of a plurality of connected nodes that the network error was detected, wherein the notification causes each node that receives the notification to change at least one transport layer parameter.

Reducing retransmission latency

A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes a plurality of ports to facilitate communication over a network. The system also includes a controller to selectively activate or deactivate ports of the system based on queue depths and additional information to improve power efficiency of the system.

Adaptive port routing

Technologies for bi-directional encryption and decryption for underlay and overlay operations are described. One network device a path-selection circuit that operates in a first mode or a second mode. In the first mode, the path-selection circuit receives a first incoming packet on a first port, sends it to a security circuitry to decrypt the first incoming packet to obtain a first decrypted packet, sends the first decrypted packet to a processing circuitry to process the first decrypted packet to obtain a first outgoing packet, and sends the first outgoing packet to a second port of the network device. In the second mode, the path-selection circuit receives a second incoming packet on a third port, sends it to the processing circuitry to de-encapsulate the second incoming packet to obtain a second outgoing packet, and sends the second outgoing packet to a fourth port of the network device.

Bi-directional encryption/decryption device for underlay and overlay operations

Apparatus for global policing of a bandwidth of a flow, the apparatus including a network device including a local policer configured to perform bandwidth policing on the flow within the network device, and a communications module configured to: send local policer state information from the local policer to a remote global policer, and receive policer state information from the remote global policer and update the local policer state information based on the remote global policer state information. Related apparatus and methods are also provided.

Global policers

A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.

Ethernet pause aggregation for a relay device

A network element includes a transmit-queue for transmitting packets from at least two sources, each source having a predefined priority level, to a headroom buffer in a peer network element. Flow-control circuitry receives from the peer network element signaling that indicates a number of credits for transmitting packets to the peer network element, manages a current number of credits available for transmission from the transmit-queue, responsive to the signaling, selects a threshold priority based on the current number of credits for the transmit-queue; and transmits packets associated with data sources of the transmit-queue that are higher in priority than the threshold priority, and refrain from transmitting other packets associated with the transmit-queue.

Head-of-queue blocking for multiple lossless queues

A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of cells of memory, one or more ports read data from the shared buffer and write data to the shared buffer, and a controller circuit selectively enables and disables cells of memory of the shared buffer based on an amount of data stored in the shared buffer. Power consumption of the shared buffer is in proportion to a number of enabled cells of memory.

Power-optimized and shared buffer

A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

Template-based packet parsing

A network element () includes circuitry and at least one port (). The at least one port is coupled to an optical fabric () including one or more optical switches () that provide optical paths between the at least one port and multiple destination nodes, at predefined time slots. The circuitry is configured to hold a schedule plan () that specifies which of the destination nodes are accessible via the optical fabric at which of the time slots, to queue packets that are destined to the destination nodes, and to transmit the queued packets via the at least one port in accordance with the schedule plan.

Time division communication via optical switch fabric

A caching system operative in conjunction with a memory and a cache, the caching system comprising a processor to use only a single hash function which compresses K bit memory addresses to H_max bit cache addresses, rather than using plural hash functions, to provide perfect hashing for each of plural applications which utilize plural respective subsets, of different sizes, from among 2{circumflex over ( )}H_max cells in the cache; and at least one logic circuit X which receives, as one of its input operands, an output, H_max bits in length, of the single hash function and which generates, as a logic circuit output, a cache address of length H_select to which at least one K-bit address is mapped where H_max<K, to ensure that input operands which differ only by H_select<=H_max bits, map to distinct hash values with no collisions.

Hash function with perfect hash component

A device, a switch, and a method of determining latency which exceeds a threshold are described. A task is enqueued and a time is determined based on two clocks. A time the task is dequeued is determined based on the two clocks. Based on the time of enqueue and the time of dequeue according to each of the two clocks, the task is identified as meeting or violating a service level agreement.

Latency detection using multiple clocks, including determination of whether latency exceeds a threshold

A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.

Controller which adjusts clock frequency based on received symbol rate

Devices, networking devices, and switches, among other things, are disclosed. An illustrative switch is disclosed to include a plurality of optical Input/Output (I/O) ports; a multi-chip module (MCM) assembly including switching circuitry and at least one chiplet that is optically coupled with one of the plurality of optical I/O ports; and a controller coupled with the at least one chiplet and configured to couple the at least one chiplet with a Quantum Key Distribution (QKD) device.

Co-packaged switch with integrated quantum key distribution capabilities

Technologies for bi-directional encryption and decryption for underlay and overlay operations are described. One network device includes multiple ports, a network processing element, a programmable path-selection circuit, and a security IC. The programmable path-selection circuit is configured to operate in a first mode in which first outgoing packets are routed to the security integrated circuit to be encrypted before sending on one of the ports, and first incoming packets, received on one of the ports, are routed to the security integrated circuit to be decrypted. The programmable path-selection circuit is configured to operate in a second mode in which second incoming packets are routed to the security integrated circuit to be encrypted before processing by the network processing element and route second outgoing packets to the security integrated circuit to be decrypted after processing by the network processing element.

An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.

Analysis of events in an integrated circuit using cause tree and buffer

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Ramat Gan, Israel

Liron Mula