Intel Corporation

University of Utah Research Foundation

Silicon Graphics, Incorporated

Liqun Cheng

Kai Cheng

Zhen Fang

John B Carter

Ravishankar Iyer

Ankush Varma

Naveen Muralimanohar

Sriram R Vangal

Lily Pao Looi

Donald K Newell

Randal Steven Passint

Adrian C Moga

Rajeev Balasubramonian

Jeffrey D Gilbert

Sadagopan Srinivasan

Donglai Dai

Faye A Briggs

Jeffrey S Wilder

Karthik Ramani

An apparatus is described that includes a plurality of processors, a plurality of cache slices and respective cache agents. Each of the cache agents have a buffer to store requests from the processors. The apparatus also includes a network between the processors and the cache slices to carry traffic of transactions that invoke the processors and/or said cache agents. The apparatus also includes communication resources between the processors and the cache agents reserved to transport one or more warnings from one or more of the cache agents to the processors that the one or more cache agents' respective buffers have reached a storage capacity threshold.

Multi-processor computing system having fast processor response to cache agent request capacity limit warning

In an embodiment of the present invention a method includes: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; and if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. Other embodiments are described and claimed.

Searching a shared cache by using search hints and masked ways

In one embodiment, the present invention includes a method for receiving a cache coherency message in an interconnect router from a caching agent, mapping the message to a criticality level according to a predetermined mapping, and appending the criticality level to each flow control unit of the message, which can be transmitted from the interconnect router based at least in part on the criticality level. Other embodiments are described and claimed.

Using criticality information to route cache coherency communications

A snoop filter maintains data coherency information for multiple caches in a multi-processor system. The Exclusive Ownership Snoop Filter only stores entries that are exclusively owned by a processor. A coherency engine updates the entries in the snoop filter such that an entry is removed from the snoop filter if the entry exits the exclusive state. To ensure data coherency, the coherency engine implements a sequencing rule that decouples a read request from a write request.

Exclusive ownership snoop filter

A method for utilizing heterogeneous interconnects comprising wires of varying latency, bandwidth and energy characteristics to improve performance and reduce energy consumption by dynamically routing traffic in a processor environment.

Microarchitectural wire management for performance and power in partitioned architectures

An apparatus and method of controlling data sharing in a shared memory computer system transfers control of a cache coherency directory (entry) to a node having control of the data. Specifically, the plurality of nodes includes a home node and a second node. The home node has given data in a cache line in its memory, and also has a directory identifying the state of the cache line. The method and apparatus thus detect a request for ownership of the cache line from the second node, and enable the second node to control the directory after receipt of the request.

Apparatus and method of controlling data sharing on a shared memory computer system

A snoop filter maintains data coherency information for multiple caches in a multi-processor system. When a new request for a memory line arrives, an entry of the snoop filter is selected for replacement if there is no available slot in the snoop filter to accommodate the new request. The selected entry is among the entries predicted to be short-lived based on a coherency state. An invalidation message is sent to the one of the caches with which the selected entry is associated.

Preselecting E/M line replacement technique for a snoop filter

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Salt Lake City, UT, United States of America

Liqun Cheng