Taiwan Semiconductor Manufacturing Comp. Ltd.

Lipu Kris Chuang

Hsin-Yu Pan

Hao-Yi Tsai

Tin-Hao Kuo

Chih-Hua Chen

Shih-Wei Chen

Han-Ping Pu

Chung-Shi Liu

Ming-Kai Liu

Ting-Chu Ko

Teng-Yuan Lo

Chien-Chang Lin

Chih-Wei Lin

Ching-Hua Hsieh

Yu-Hsiang Hu

Chung-Hao Tsai

Ming Hung Tseng

Tsung-Hsien Chiang

Sen-Kuei Hsu

Tzu-Sung Huang

Chao-Wei Li

Yi-Che Chiang

Kai-Ming Chiang

Ming-Chang Lu

Ching Yao Lin

Wei Lun Tsai

A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.

Staggered metal mesh on backside of device die and method forming same

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

Stacked memory cube with integrated thermal path for enhanced heat dissipation

Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.

Semiconductor package with thermal relaxation block and manufacturing method thereof

A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

Integrated circuit package and method

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

Semiconductor package and method of manufacturing the same

Memory device and manufacturing method thereof

Manufacturing method of semiconductor package including thermal conductive block

A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure. The thermally conductive material is disposed on the second redistribution structure, among the second semiconductor dies and overlying the through insulator vias. The thermally conductive material has a thermal conductivity larger than that of the encapsulant.

Memory module, semiconductor package including the same, and manufacturing method thereof

A semiconductor device includes a bottom package, a top package, and a heat dissipating structure. The bottom package includes a redistribution structure, and a die disposed on a first surface of the redistribution structure and electrically connected to the redistribution structure. The top package is disposed on a second surface of the redistribution structure opposite to the first surface. The heat dissipating structure is disposed over the bottom package, and includes a thermal relaxation block. The thermal relaxation block contacts the redistribution structure and is disposed beside the top package.

Semiconductor package including thermal relaxation block and manufacturing method thereof

Semiconductor packages are provided. One of the semiconductor packages includes a first sub-package and a second sub-package. The first sub-package includes a first die, a graphite oxide layer on the first die and an encapsulant encapsulating the first die and the graphite oxide layer. The second sub-package is stacked on and electrically connected to the first sub-package, and includes a second die. The graphite oxide layer is disposed between the first die and the second die.

Semiconductor packages

Semicondcutor package and method of manufacturing the same

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Hsinchu, Taiwan

Lipu Kris Chuang