Marvell Asia Pte., Ltd.

Sonics, Incorporated

Marvell International Limited

Marvellworld Trade Ltd.

Liping Guo

Salil Suri

Scott Furey

Yingdong Li

Doddaballapur N Jayasimha

Jeremy Chan

Jun Zhu

Joseph Jun Cao

Chih-Lung Liu

A switch device is configured to communicate with a plurality of hosts and a solid state drive (SSD). The plurality of hosts includes a first host and a second host. The switch device receives a first memory access command from the SSD, the first memory access command including an indication of the first host to indicate the first memory access command is intended for the first host. The switch device uses the indication of the first host in the first memory access command to route the first memory access command to the first host. The switch device removes the indication of the first host from the first memory access command prior to sending the first memory access command to the first host via a peripheral computer interface express (PCIe) interface of the switch device.

Switch device for interfacing multiple hosts to a solid state drive

In a system with multiple host computers and one or more single-port non-volatile memory devices, a non-volatile memory switch receives memory transaction messages from different root complexes corresponding to the multiple host computers. Each of at least some of the memory transaction messages includes a host identifier that identifies a root complex from which the memory transaction was received. The non-volatile memory switch generates modified memory transaction messages at least by changing host identifiers within memory transaction messages to a common value indicative of a single root complex to present to the one or more single-port non-volatile memory devices the different root complexes as the single root complex. The non-volatile memory switch maintains associations of memory transaction messages with corresponding ones of the different root complexes, and sends the modified memory transaction messages to the one or more single-port non-volatile memory devices.

Non-volatile memory switch with host isolation

The present disclosure describes apparatuses and methods for automatically mapping virtual functions to storage media to enable single root input output virtualization. A storage media switch manages access to virtual functions that execute behind a storage media interface managed by the switch. The switch includes a host interface through which the switch receives host commands. The switch determines virtual function identifiers associated with the host commands and automatically selects the virtual functions of the storage media based on the virtual function identifiers. The switch executes the host commands over the storage media interface using the virtual functions, and after execution, responds via the host interface to each of the host commands. By automatically mapping virtual functions in this way, the switch automatically enables single root input output virtualization of storage media, including storage media that is without native support for input output virtualization.

Enabling virtual functions on storage media

The present disclosure describes apparatuses and methods for virtualizing isolation areas of solid-state storage media. In some aspects, a storage media accelerator determines, via a storage media interface, a geometry of solid-state storage media. The accelerator selects, based on the geometry, an area of the solid-state storage media as an isolated unit of storage. A physical address of the isolated unit of storage is then mapped to a virtual address. The accelerator exposes, via the virtual address, the isolated unit of storage through a host interface to enable host access of the isolated unit of storage. The accelerator may also remap the isolated unit of storage to other areas of the solid-state storage media without host interaction. By so doing, the accelerator may provide virtualized isolation and partitioning functionalities to a host, while efficiently handling lower-level storage media functions, such as wear leveling and load balancing, without host involvement.

Virtualizing isolation areas of solid-state storage media

A NVM switch has been designed that allows multiple hosts to simultaneously and independently access a single port NVM device. While this active-active multi-host usage configuration allows for a variety of uses of lower cost single port NVM device, an issue with one of the hosts can delay or block transactions between the other host and the NVM device. The NVM switch includes logic that isolates activity of the multiple hosts despite logic of the switch being shared across the hosts. When the switch detects an issue with one host ('error host'), the switch clears the in-flight commands of the error host and flushes data of the error host. Likewise, the NVM switch ensure proper communication of error reporting from attached NVM devices to the multiple hosts.

A non-volatile memory express (NVMe) switch is located in between a host and storage. A first storage access command is received from a host via a peripheral computer interface express (PCIe) interface to access the storage. The first storage access command conforms to NVMe and the storage comprises two or more solid-state drives (SSDs). A respective second storage access command is sent to the two or more SSDs based on the first storage access command. A respective completion is received from each of the two or more SSDs based on the respective second storage access command. A completion is sent to the host via the PCIe interface based on the received completions from each of the two or more SSDs.

Managed switching between one or more hosts and solid state drives (SSDs) based on the NVMe protocol to provide host storage services

A method includes, in at least one aspect, determining a relative delay of a signal path with respect to a timing budget; determining that the signal path is active; determining a value of a voltage being supplied to the signal path; and causing an adjustment in the voltage being supplied to the signal path based on the relative delay, the signal path being active, and the value of the voltage being supplied to the signal path.

Universal adaptive voltage scaling system

A method includes receiving flits forwarded from an upstream router into a first input virtual channel (VC) associated with an input port. The flits are associated with packets originated from a first Intellectual Property (IP) core and forwarded to a second IP core. The flits are stored in a VC storage associated with the first input VC. The method further includes performing link width conversion based on a width of the flits being different from a width of an output port. Link width conversion includes accumulation of the flits when the width of the output port is wider and unpacking of the flits when the width of the output port is narrower. Credits are generated based on the flits being forwarded from the first input VC to the output port. The credits are sent to the upstream router to enable receiving more flits from the upstream router.

Credit flow control scheme in a router with flexible link widths utilizing minimal storage

In some implementations, a system includes a universal adaptive voltage scaling monitor (UAVSM) and an adaptive voltage scaling (AVS) controller. The UAVSM is configured to delay a first signal generated by a signal path by an adjustable time period, compare the delayed first signal and a second signal associated with the signal path, and provide an error signal indicating a result of the comparison, where the error signal is asserted when the result of the comparison indicates that the delayed first signal is different from the second signal. The AVS controller is configured to provide a first control signal indicating that the voltage is to be increased when the received error signal is an asserted error signal, and provide a second control signal indicating that the voltage is to be decreased when the received error signal is an unasserted error signal and the signal path is active.

A method for generating headers in packetized protocols for a flexible routing network for a Network on a Chip (NoC) architecture includes generating packets based on transmission traffic received from an initiator or a target connected to a routing network that connects disparate initiators and targets. Logic to generate the packets is in an interface located between the initiator or the target and the routing network. A header portion of a packet is variable in length and includes a header payload and header control information. Each of the header portion and the body portion includes one or more standard sized transmission units. The size of the transmission units and width of the header payload are determined by logic included in the interface. The width of the header payload is determined based on orthogonal groups with each of the orthogonal groups being associated with targets sharing an initiator thread.

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Palo Alto, CA, United States of America

Liping Guo