Omnivision Technologies, Inc.

Liping Deng

Tiejun Dai

Yingkan Lin

Liang Zuo

Yu-Shen Yang

Bi Yuan

Zhiqiang Song

Rui Wang

Yi Liu

Yuxin Wang

Zejian Wang

Jingzhou Zhang

Fan Zhu

Pengting Zhang

Sohei Manabe

Zheng Yang

Min Qu

Tianjia Sun

Wei Zheng

Chun-Ming Tang

Chun-Hsiang Chang

Xueqing Wang

Zhihao Xu

Chien-Chen Chen

Tie Jun Dai

Quifeng Jin

Hongtao Yao

Haidong Guo

Chieh-Chien Lin

Zheng Wei

An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse.

Current injection for fast ramp start-up during analog-to-digital operations

A pixel cell includes a photodiode to accumulate image charge. A global shutter transistor is coupled to the photodiode to reset the image charge in the photodiode in response to a global shutter control signal. A global shutter control signal generator circuit generates the global shutter control signal to have a first value signal or a second value signal. The first value signal is coupled to turn on the global shutter transistor to reset the photodiode. The second value signal controls the global shutter transistor to be in a low leakage off mode. A supply circuit is coupled to provide the second value signal to the global shutter control signal generator circuit. The supply circuit includes a variable filter circuit coupled to an output of the supply circuit to selectively vary a bandwidth of the second value signal in response to a bandwidth select signal.

Image sensor global shutter supply circuit with variable bandwidth

An image sensor pixel noise measurement circuit includes a pixel array on an integrated circuit chip. The pixel array includes a plurality of pixels including a first pixel to output a first image data signal, and a second pixel to output a second image data signal. A noise amplification circuit on the integrated circuit chip is coupled to receive the first and second image data signals from the pixel array. The noise amplification circuit is coupled to output an amplified differential noise signal in response to the first and second image data signals received from the pixel array. A fast Fourier transform (FFT) analysis circuit on the integrated circuit chip is coupled to transform the amplified differential noise signal output by the noise amplification circuit from a time domain to a frequency domain to analyze a pixel noise characteristic of the pixel array.

Image sensor pixel noise measurement

A pixel circuit includes a photodiode, and a transfer transistor coupled to the photodiode. A floating diffusion is coupled to the transfer transistor coupled to transfer image charge from the photodiode to the floating diffusion. An amplifier circuit includes an input coupled to the floating diffusion, an output coupled to generate an image data signal of the pixel circuit, and a variable bias terminal coupled to receive a variable bias signal. A reset switch is coupled between the output and input of the amplifier circuit to reset the amplifier circuit in response to a reset signal. A variable bias generator circuit is coupled to generate the variable bias signal in response to a reset signal to transition the variable bias signal from a first bias signal value to a second bias signal value in response to a transition of the reset signal from an active state to an inactive state.

Imaging sensor with amplifier having variable bias and increased output signal range

An example current generator may include a low dropout regulator (LDO) coupled to receive a reference voltage and provide a reference current in response, where the LDO adjusts a current level of the current reference in response to a calibration signal. A current controlled oscillator coupled to receive a reference current copy from the LDO and generate an oscillating signal in response, where a period of the oscillating signal is based at least in part on a level of the reference current copy. A pulse generator coupled to provide an adjustable pulse signal. A counter coupled to determine a number of periods of the oscillating signal occurring during a duration of the pulse signal, and provide a control signal indicative of such, and a digital calibration circuit coupled to receive the control signal and provide the calibration signal to the LDO in response.

Current generator

Apparatuses and methods for reducing vertical fixed pattern noise in imaging systems are disclosed herein. An example apparatus may include an analog dithering circuit coupled to randomly add an offset voltage to a first reference voltage in response to a random binary signal during an analog to digital conversion operation, and a ramp generator circuit coupled to receive the first reference voltage, and provide a second reference voltage in response, wherein the randomly added offset voltage to the first reference is also present in the second reference voltage.

Analog dithering to reduce vertical fixed pattern noise in image sensors

A readout circuit for use in an image sensor includes a system ramp generator coupled to generate a system ramp signal. A plurality of analog-to-digital converters is coupled to a plurality of column bitlines from a pixel array to receive corresponding analog column image signals. An isolation ramp buffer is coupled between the system ramp generator and the analog-to-digital converters. The isolation ramp buffer includes a single input to receive the system ramp signal, and a plurality of isolated outputs. Each of the isolated outputs is coupled to provide an isolated column ramp signal to a corresponding analog-to-digital converter. Each of the of analog-to-digital converters is coupled to generate a corresponding digital column image signal in response to the corresponding analog column image signal and corresponding isolated column ramp signal.

Horizontal banding reduction with ramp generator isolation in an image sensor

A pixel cell includes a photodiode disposed in a semiconductor material to accumulate image charge in response to light. A global shutter transistor is disposed in the semiconductor material and is selectively resets the image charge in the photodiode in response to a global shutter control signal. A global shutter control signal generator circuit is coupled to generate the global shutter control signal to have a first value, a second value, and a third value. The first value of the global shutter control signal is coupled to turn on the global shutter transistor to reset the photodiode. The third value of the global shutter control signal is coupled to control the global shutter transistor to be in a low leakage off mode. The second value of the global shutter control signal is between the first and third values and is turns off the global shutter transistor.

Global shutter control signal generator with reduced driving requirements

A power supply noise measurement circuit includes a multiphase filter coupled to receive a power supply signal. The multiphase filter is coupled to output a first filtered power supply signal for a first phase, and a second filtered power supply signal for a second phase. A multiphase amplifier is coupled to the multiphase filter to sample offset voltages in response to the first filter power supply signal during the first phase to set up DC operation points in the multiphase amplifier, and generate an amplified power supply noise signal during the second phase. An overshoot detector is coupled to the multiphase amplifier to detect overshoot events in the amplified power supply noise signal, and an undershoot detector is coupled to the multiphase amplifier to detect undershoot events in the amplified power supply noise signal.

Image sensor power supply noise detection

A ramp generator for use in readout circuitry includes an integrator coupled to receive a ramp generator input reference signal to generate a reference ramp signal coupled to be received by an analog to digital converter. A power supply compensation circuit that is coupled to generate the ramp generator input reference signal includes a delay circuit including a variable resistor and a filter capacitor coupled to receive a power supply signal. The variable resistor is tuned to match a delay ripple from the power supply to a bitline output. A capacitive voltage divider is coupled to the delay circuit to generate the ramp generator input reference signal. The capacitive voltage divider includes a first variable capacitor coupled to a second variable capacitor that are tuned to provide a capacitance ratio that matches a coupling ratio from the power supply to the bitline output.

Image sensor power supply rejection ratio improvement through ramp generator in continuous time readout circuitry

A readout circuit for use in an image sensor includes a sense amplifier circuit coupled to a bitline to sense analog image data from a pixel cell of the image sensor. An analog to digital converter is coupled to the sense amplifier circuit to convert the analog image data to digital image data. A ramp generator circuit is coupled to generate a first ramp signal. The analog to digital converter is coupled to generate the digital image data in response to the analog image data and the first ramp signal. A first capacitive voltage divider is coupled to the ramp generator. The first capacitive voltage divider is coupled to reduce an output voltage swing of the first ramp signal coupled to be received by the analog to digital converter to reduce noise in the first ramp signal.

Ramp generator for low noise image sensor

A ramp generator includes a supply voltage sampling circuit coupled to sample a black signal supply voltage during a black signal readout, and an image signal supply voltage of the pixel cell during an image signal readout of a pixel cell. A first integrator circuit receives a buffered reference voltage, and an output of the supply voltage sampling circuit. First and second switches are coupled between the first integrator circuit and a first capacitor to transfer a signal representative of a difference between the image signal supply voltage and the black signal supply voltage to the first capacitor. A second integrator circuit is coupled to the first capacitor to generate an output ramp signal coupled to be received by an analog to digital converter. A starting value of the output ramp signal is adjusted in response to the difference between the image signal and the black signal supply voltage.

Image sensor power supply rejection ratio noise reduction through ramp generator

An image sensor read out circuit includes a first current mirror circuit in which a second current conducted through a second current path is controlled in response to a first current conducted through the first current path. The second current is conducted through an amplifier transistor of a pixel circuit. A first current source is coupled to the first current path to provide a substantially constant current component of the first current. A second current source is coupled to a power supply rail of the pixel circuit and coupled to the first current path to provide a ripple current component of the first current. The ripple current component provided by the second current source is responsive to a ripple in the power supply rail. The first current is responsive to a sum of the currents from the first and second current sources.

Feed-forward technique for power supply rejection ratio improvement of bit line

A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.

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Cupertino, CA, United States of America

Liping Deng