Freescale Semiconductor,inc.

Nxp Usa, Inc.

Lipeng Cao

Hector Adrian Sanchez

Khoi Mai

Gayathri Bhagavatheeswaran

Kenneth R Burch

Tommi M Jokinen

Carol G Pyron

Ramon V Enriquez

Khoi B Mai

A thermal sensor system including at least one thermal sensor, a voltage control network, a current gain network, a current compare sensor, and a controller. The voltage control network applies reference and delta voltage levels to a thermal sensor, which develops reference and delta current signals. The current gain network is used to adjust current gain. The current compare sensor is responsive to the reference and delta current signals and provides a comparison metric. The controller selects a temperature subrange and controls the current gain network to adjust the gain of the delta current signal to determine a gain differential value indicative of the temperature. The controller may select from among different sized thermal sensors, current mode gain values, and control voltages corresponding with each of multiple temperature subranges. Any one or more of these parameters may be adjusted to adjust an operating point for selecting a corresponding temperature subrange.

Thermal sensor system and method based on current ratio

A method and circuit for providing on-chip measurement of the delay between two signals includes first and second delay chains () having different delay values connected to sampling latches (-) which each include a data input coupled between adjacent delay elements of the first delay chain and a clock input coupled between adjacent delay elements of the second delay chain, thereby capturing a high precision delay measurement for the signals.

High precision single edge capture and delay measurement circuit

A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal of the phase locked loop. The phase detector provides a pulse having a width indicative of the phase difference. A phase measurement module determines a digital value based on the pulse width. Accordingly, the digital value provides an indication of the phase difference between the reference clock signal and the output clock signal. A series of the digital values can be recorded to indicate how the phase difference varies over time, thereby providing a useful characterization of device behavior.

Phase locked loop device and method thereof

A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.

Phase-locked loop system with a phase-error spreading circuit

Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions of the input signal at a plurality of taps. The interface circuit, which is characterized by an inherent interface circuit delay, passes one of the delayed versions to an interface circuit output in response to a control signal. The tap selection circuit determines a finally-identified tap of the plurality of taps by determining an initially-identified tap at which a delayed version of the input signal most closely has a desired alignment with the input signal, and by identifying the finally-identified tap in the control signal as a tap that occurs earlier in the delay line than the initially-identified tap. This compensates for the inherent delay of the delay stage.

Multiple-stage, signal edge alignment apparatus and methods

A modulus divider controller coupled to a modulus divider for generating a synthesized clock from a reference clock, wherein the modulus divider generates a divided clock, is provided. The modulus divider controller may further include a first binary stream switching circuit having a first output and a second output. The first binary stream switching circuit may further have a logic low input and a logic high input and a first switching input corresponding to a most significant bit of a count generated by a synchronous counter, wherein the synchronous counter counts the divided clock. The first binary stream switching circuit may further have a second switching input corresponding to a least significant bit of a division control word, wherein the division control word specifies a fractional division ratio for the synthesized clock.

Binary stream switching controlled modulus divider for fractional frequency synthesis

A process for deriving a power transfer function of a circuit. The power transfer function can be used to represent the real time power consumption of a circuit based on the status of the inputs. In one embodiment, the power transfer function is derived from frequency domain analysis of signals applied to the inputs of a circuit during tests of the circuit. In one embodiment, the inputs of the circuit are grouped in groups based on a commonality of power consumption of the signals. The inputs may be grouped by clustering squared coherencies associated with the inputs. The transfer function may be implemented in a power monitoring circuit having inputs coupled to the inputs of the circuit to provide a real time estimation of power consumption of the circuit.

Power consumption estimation

One use for delay adjustment circuit (), coarse-grain delay offset circuit (), and fine-grain delay synthesis circuit () may be as part of a delay replication circuit () used to replicate the frequency versus voltage behavior of an integrated circuit (). Also, a circuit () and method for determining optimal power and frequency metrics of integrated circuit () is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.

Circuit and method for determining optimal power and frequency metrics of an integrated circuit

Delay circuitry and method therefor

One use for delay adjustment circuit (), coarse-grain delay offset circuit (), and fine grain delay systhesis circuit () may be as part of a delay replication circuit () used to replicate the frequency versus voltage behavior of an integrated circuit (). Also, a circuit () and method for determining optimal power and frequency metrics of integrated circuit () is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.

Method for determining programmable coefficients to replicate frequency and supply voltage correlation in an integrated circuit

Behavior of an electrical circuit can be modeled using a trained neural network. For example, using one or more neural networks, power consumption, including leakage power and switching energy, can be estimated. Also, a profile of current versus time can be generated for the electrical circuit. A hierarchy of neural networks may be used to model the circuit at different levels. In one embodiment, a circuit behavior is modeled using one or more neural networks, cluster values, and cluster probabilities.

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Austin, TX, United States of America

Lipeng Cao