Dell Products Inc.

Lip Vui Kan

Young Hwan Jang

Sumanth Vidyadhara

Geroncio Ong Tan

Nicholas Diciurcio Grobelny

Ricardo Luis Martinez

Merle Wood, Iii

Wei Cheng Yu

Chai Im Teoh

Shun-Tang Hsu

Neeraj Kumar Pant

An information handling system is configured to support first and second boot sequences, which invokes first and second bootloaders respectively. The bootloaders may be stored in an NVMe storage boot partition. Each bootloader may be associated with a corresponding encryption key generated by a trusted platform module, which may seal the first and second keys in accordance with one or more measurements taken during the respective boot sequences. The system determines whether a boot sequence in progress comprises is to invoke the first or second bootloader. The system then unseals the appropriate encryption key to access the appropriate bootloader. The first bootloader may be a host OS bootloader and the second bootloader may be for a recovery resource invoked when the host OS fails to load. The recovery resource may enables BIOS to connect to a remote store and download an image via a HTTP mechanism.

Trusted platform module protection for non-volatile memory express (NVMe) recovery

Establishing a diagnostic OS for an information handling system platform performing a UEFI BIOS boot to place the platform in a pre-OS state. Upon detecting a particular POST error and/or a platform configuration policy, an embedded OS kernel may be launched into a DRTM-authenticated measured launch environment (MLE). Additional objects for the diagnostic OS may be downloaded. The additional objects may include an initial ramdisk (initrd) module and one or more applications specific to the particular diagnostic OS. The diagnostic OS may be launched as follows: for each diagnostic OS application, launching the application and extending a measurement of the application into a DRTM PCR. Launching the diagnostic OS may include launching an initrd module and extending a measurement of the initrd module into the DRTM PCR. A measurement of embedded OS kernel may be extended into the TPM and the embedded OS kernel may validate the UEFI BIOS sequence.

Chained loading with static and dynamic root of trust measurements

Reducing power consumption at an information handling system (IHS), including identifying a first data set associated with a first application, and a second data set associated with a second application; storing the first data set at a first physical storage device, and storing the second data set at a second physical storage device; reducing a power consumption of a storage device system, including: determining that the first and second applications are out-of-focus with respect to an operating system (OS) of the IHS, and in response, maintaining a low power state of the first and the second physical storage devices; detecting that the first application is in-focus with respect to the OS of the IHS, and in response, adjusting a power state of the first physical storage device from the low power state to an active power state while maintaining the low power state of the second physical storage device.

Reducing power consumption of memory devices at an information handling system

Systems and methods that may be implemented to automatically sense and verify proper mated orientation of a removable BGA package relative to a mating pad array (e.g., of a BGA socket) prior to supplying power to the BGA package. A removable BGA package may be provided with first and second symmetric pins so as to present different respective circuit states on opposing sides of a center point of its BGA package pin array, such that proper orientation of the BGA package occurs only when a designated one of the first and second symmetric pins is mated with a designated pad of the mating pad array. A programmable integrated circuit may in turn sense the circuit state presented at the designated pad to verify proper orientation of the mated BGA package based on the sensed circuit state presented at the designated pad, and may take one or more designated actions based on whether or not proper orientation of the mated BGA package is verified.

Systems and methods for automatically verifying BGA package orientation

Systems and methods that may be implemented for that may be implemented to compensate for NAND flash memory voltage threshold (Vth) shift by using one or more designated calibration wordlines that are programmed into the NAND flash memory with a pre-defined data pattern. In one example configuration, the disclosed systems and methods may be automatically implemented by a SSD controller when needed to compensate for flash memory voltage threshold (Vth) shift that occurs, e.g., due to NAND memory cell charge loss due to power-off data retention over an extended period of time.

Systems and methods of implementing a calibration wordline to compensate for voltage threshold shift in NAND flash memory

A preboot module of BIOS may be configured to create a partition mapping table for namespace identifiers of sub-partitions of a boot partition, determine a configuration policy for the information handling system, store the configuration policy in a partition of non-volatile memory, launch execution of an embedded operating system kernel, and communicate the partition mapping table to the embedded operating system kernel based on the configuration policy, such that the embedded operating system kernel is enabled to load the configuration policy from the non-volatile memory and load and execute one or more applications based on the partition mapping table and the configuration policy.

Systems and methods for securely launching an embedded operating system using non-volatile memory namespace identifier mapping

A host memory buffer is configured as a write cache for prioritizing read operations. When a peripheral device (such as a solid-state drive) receives a mixture of read requests and write requests, the write requests may be suspended or deferred to first execute the read requests. The write requests may be cached to the host memory buffer, thus allowing the peripheral device to process the read requests for relatively immediate response. Once the read requests are completed, the peripheral device may begin executing a queue of the write requests stored to the host memory buffer. This caching strategy results in a thirty percent (30%) improvement in drive performance.

Information handling system having improved host memory buffer for input/output requests

An information handling system includes a memory array and a memory controller. The memory array stores data within the information handling system. The memory controller writes the data to the memory array. The memory controller also determines whether a temperature of the memory array is above a threshold temperature. The memory controller tags a plurality of memory locations within the memory array written with data while the temperature is above the threshold temperature. While a refresh operation is being executed, the memory controller determines whether the temperature of the memory array is below the threshold temperature. In response to the temperature of the memory array being below the threshold temperature and while the refresh operation is being executed, the memory controller rewrites the data in the tagged memory locations within the memory array.

System and method for refreshing data for integrity protection at a thermal excursion event

A method and information handling system, including a solid state drive (SSD) memory device having NAND flash memory and an SSD controller to execute instructions of an SSD adaptive profiling engine for random access memory (RAM) cache optimization, are disclosed. The SSD controller is configured to cache a partial flash translation layer (FTL) table in RAM including look-up addresses corresponding to LBA segments in the NAND flash memory having access counts reflecting SSD I/O operations. The SSD controller is further configured to detect an outlier LBA segment having look-up addresses in the cached, partial FTL table, wherein the outlier LBA segment has an I/O access counts at a threshold level below the mean of access counts of other LBA segments represented in the partial FTL table, and to evict the LBA segment look-up address of the outlier LBA segment from the cached portion of the FTL table. The partial FTL table may expanded to accommodate additional look-up addresses when no outlier LBA segments exist. A portion of the RAM not used for caching the partial FTL table may be used as a prefetch cache for I/O access operations.

System and method for adaptive optimization for performance in solid state drives based on segment access frequency

In some examples, a circuit includes (1) a voltage regulator, (2) a voltage divider that includes a first resistor, a second resistor, and a third resistor, and (3) a device that includes a first pin, a second pin, and a third pin. In the device, when the first pin is connected to the first resistor and to a ground (the second and third pin are unconnected), a voltage input of the device receives a first voltage from the voltage regulator. When the second pin is connected to the second resistor and to the ground (the first and third pin are unconnected), the voltage input receives a second voltage from the voltage regulator. When the third pin is connected to the third resistor and to the ground (the first and second pin are unconnected), the voltage input receives a third voltage from the voltage regulator.

Self-configuring integrated circuit device

Methods and systems that may be implemented for managing data migration from relatively higher performance and higher endurance solid state non-volatile memory media to relatively lower performance and lower endurance solid state non-volatile memory media. The disclosed methods and systems may be implemented to reduce write amplification that occurs to solid state non-volatile memory media of a memory device by using frequency of LBA update as a parameter for controlling and optimizing data eviction from a relatively higher performance and higher endurance input buffer section in the receiving front of a memory device to a relatively lower performance and lower endurance main memory section of the same memory device.

Methods and systems for managing data migration in solid state non-volatile memory

A method and information handling system and having a solid state drive (SSD) memory device including NAND flash memory with an SSD controller to execute instructions of an SSD adaptive profiling engine for RAM cache optimization and configured to cache a partial FTL table in RAM including look-up addresses corresponding to LBA segments in the NAND flash memory having access counts reflecting SSD I/O operations. The method and system further configured to determine whether the SSD memory device operation is write intensive (or read intensive) from assessment of stored read access counts and write access counts and further determine whether to load a partial FTL table into RAM cache and use remaining unoccupied RAM space for a data cache to enhance the SSD memory device operations.

System and method for adaptive optimization for performance in solid state drives based on read/write intensity

A method and information handling system configured to executing instructions of an SSD dynamic optimization buffer switching system and configured to detecting SSD storage capacity utilization via an SSD controller. The method and information handling system further configured to reallocate buffer capacity from write acceleration buffer capacity to garbage collection buffer capacity to increase buffer availability for garbage collection when SSD storage capacity utilization exceeds a threshold level.

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Singapore, Singapore

Lip Vui Kan