Intel Corporation

Lior Gil

Michael Zelikson

Kosta Luria

Vadim Goldenberg

A supply voltage may be set using a local voltage regulator, such as a Digital Linear Voltage Regulators (DLVR). A DLVR may include a compensator, and the performance of the compensator may be affected by a dropout (DO) voltage. To improve the performance of a compensator, a number of compensator calculations may be pre-calculated to reduce the complexity of remaining real-time computations and enable compensator calculations to be completed within a single DLVR clock cycle. A DLVR may include a sense filter, and the DLVR transfer function (TF) may be modified using dynamic shaping of open loop gain and pole locations of a sense filter. The DO range associated with the DLVR TF may be changed according to a monitored DO(t) to reduce the sensitivity of a domain VMIN on dropout, which reduces power consumption, increases performance, and enables simplification of test flows.

DLVR-supplied logic domain operational voltage optimization

Some embodiments include an apparatus including a first node in a voltage regulator, a second node in the voltage regulator, and a power stage to receive a first voltage from the first node and provide a second voltage at the second node. The power stage includes a first circuit path and a second circuit path coupled in parallel with each other between the first and second nodes. The first circuit path includes a first number of at least one transistor coupled between the first and second nodes. The second circuit path includes a second number of at least one transistor between the first and second nodes. Wherein the first number is unequal to the second number.

Digital voltage regulator including mixed-stack power stage

The circuits and methods described herein provide technical solutions for technical problems facing power driver circuits. To reduce or eliminate effects associated with a gate capacitance discharge current and inconsistent effective V, the discharge process may be split into two phases. During a first phase, the transistor gate charge is drained into ground through a large path gate. The ground (GND) features a very low impedance, hence the resulting δV(t)|is negligible even for high discharge currents. The transistor gate node voltage (V) is constantly monitored, and the discharge process switches from the first phase to the second phase when Vtransgresses a bias voltage threshold based on the target value of V. To switch from the first phase to the second phase, the current path into GND is cut by switching its path gate to an OFF state, and an alternative path is enabled between transistor gate charge and V.

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Haifa, Israel

Lior Gil