Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Lior Avital

Mahim Raj Gupta

Alexander Bazarsky

Niles Yang

Tomer Tzvi Eliash

Michael Micha Ionin

Piyush Girish Sagdeo

Lola Grin

Ramkumar Subramanian

Itay Busnach

Lior Bublil

Aspects of a storage device are provided for handling GBBs with defects between global interconnects and local word lines. The storage device includes a plurality of blocks each including a plurality of word lines, a plurality of interconnects within an interconnect set and between multiple ones of the blocks, volatile memory, and a controller. The controller determines a logical address pattern associated with the multiple ones of the blocks respectively including a program failure, determines whether the logical address pattern is associated with the interconnect set for the multiple ones of the blocks, determines a common word line associated with the program failures in the multiple ones of the blocks, un-marks these blocks as GBBs, and refrains from programming the common word line during respective program operations in the multiple ones of the blocks. Thus, blocks may be reclaimed, defective word line(s) isolated, and likelihood of read-only modes reduced.

System recovery during CGI-WL defect

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a power loss event has occurred, determine that one or more blocks are in an erased state, examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block, and place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block. The controller is further configured to determine a first bit count of page0 for a SLC voltage for the block, determine a second bit count of page1 for a TLC voltage for the block, and classify the block as either a SLC erased block or a TLC erased block.

Block erase type detection using bit count check

A method is provided that includes performing a post-write read operation on a block of memory cells that includes a select gate transistor, and based on results of the post-write read operation selectively performing a select gate maintenance operation on the select gate transistor.

Apparatus and methods for merging post-write read and select gate maintenance operations

Growing community of inventors

Kfar Saba, Israel

Lior Avital