International Business Machines Corporation

Lior Arie

Israel A Wagner

Noam Jungmann

Elazar Kachir

Hezi Shalom

Lidar Herooti

Uri Moshe

Derrick Merrill Smith

In an approach utilizing static analysis, a processor receives a netlist for an integrated circuit. For at least one node of the integrated circuit in the netlist, a processor calculates (i) a total capacitive load of the respective node and (ii) a minimum required driver size. For a driver of the respective node, a processor (i) determines an effective driver size of the driver based on at least a number of fins of the driver and (ii) determines that the effective driver size exceeds the minimum required driver size multiplied by a predefined sizing margin. A processor, responsive to determining that the effective driver size exceeds the minimum required driver size multiplied by the predefined sizing margin, generates a report, where the report includes at least the driver and a suggestion to reduce the effective size of the driver.

Power reduction in very large-scale integration (VLSI) systems

A voltage-controlled delay line including a clipper configured to produce a clipped input voltage from an input voltage, an oscillator configured to produce a strobe pulse train that is initiated by the clipped input voltage, and a divider module configured to divide the strobe pulse train and produce an output voltage from the divided strobe pulse train.

Self-timed, log-space, voltage-controlled delay line

A method in a computer-aided design system for generating a functional design model of a static random access memory is described herein. The method comprises generating a functional representation of a first local evaluation logic coupled to a first set of consecutive global bit lines (GBLs) and a first set of local bit lines (LBLs), the first local evaluation logic comprising a plurality of devices. The method further comprises generating a functional representation of a second local evaluation logic communicatively coupled to the first local evaluation logic via the devices; the second local evaluation logic is coupled to a second set of consecutive GBLs and a second set of LBLs. In addition, the second set of consecutive GBLs consecutive to the first set of consecutive GBLs, the first and second evaluation logics to generate signals from the LBLs such that one GBL is to be active at any point in a read or write cycle and the other GBLs are not concurrently active.

Structure for static random access memory

A design structure can include elements that, when processed in a semiconductor manufacturing facility, produce an SRAM that includes a first local evaluator coupled to a first global bit line (GBL) and a first set of local bit lines (LBLs). The SRAM can also include a second local evaluator communicatively coupled to the first local evaluator. The second local evaluator is coupled to a second GBL and second set of LBLs. The second GBL is consecutive to the first GBL. The first and second evaluators are to generate signals from the LBLs such that one GBL of a combined first and second GBLs is active at any point in a read or write cycle.

Growing community of inventors

Haifa, Israel

Lior Arie