Qualcomm Incorporated

Cisco Technology, Inc.

Chipx Incorporated

Nds Corporation

Lior Amarilio

Sharon Graif

Amit Gil

Chaim Shen-Orr

Uri Bear

Alexander Khazin

Lalan Jee Mishra

Reuven Elbaum

Tomer Rafael Ben-Chen

Yonatan Shlomovich

Zvi Shkedy

Yigal Shapiro

Oded Schnitzer

Richard Dominic Wietfeldt

Radu Pitigoi-Aron

Nir Gerber

Terrence Brian Remple

Nir Strauss

Yuval Corey Hershko

Jason R Gonzalez

Suman Kumar

Sandeep Kumar

Meital Zangvil

Boaz Moskovich

Mark Gakman

Yoav Segal

Yiftach Benjamini

Assaf Shacham

Joseph Robert Fitzgerald

Meysam Azin

Mouna Elkhatib

Yossi Amon

Zeev Shusterman

Gilad Meir Sthoeger

Navdeep Mer

Jin-sheng Wang

Kishalay Haldar

Le Wang

Michael Zilbershtein

Doron Zehavi

Ophir Nadir

Elie H Massabki

Nileena Pathalayi Alakandy

Syed Naseef

Oren Reiss

Puxuan Dong

Alexander Golubitski

Oren Nishry

Haim Hagay Haller

Felix Kolmakov

Ghanashyam Prabhu

David Schkolnik

Chaim D Shen-Orr

High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

High-speed communication link with self-aligned scrambling

Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.

Fast activation during wake up in an audio system

Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

I2C bus architecture using shared clock and dedicated data lines

Systems and methods for essentially continuous audio flow for Internet of Things (IoT) devices during power mode transitions contemplate an audio bus, such as a SOUNDWIRE audio bus, to maintain an audio stream during a clock transition without having to tear down the audio stream as a new clock becomes active on the audio bus. By preserving the audio stream during such a transition, gaps in the audio are avoided resulting in better performance and end user experience.

Audio flow for internet of things (IOT) devices during power mode transitions

Systems, methods, and apparatus are configured to enable a receiver to provide feedback. A feedback mechanism enables a transmitting device to identify the provider of feedback for a multicast transmission, and the feedback transmitted by one or more individual receivers of the multicast transmission. A method includes receiving a multicast write command from the serial bus in a first datagram, writing a data byte received in a first data frame of the first datagram to a register address identified by the first datagram, and providing device-specific feedback regarding the first datagram in a multibit slot within the second data frame. The multibit slot is one of a plurality of sequential multibit slots defined for the second data frame. Each multibit slot in the plurality of sequential multibit slots may provide device-specific feedback from one receiving device addressed by the multicast write command.

Group slave identifier time-multiplexed acknowledgment for system power management interface

Systems and methods for scrambling data-port audio in SOUNDWIRE&#x2122; systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

Scrambling data-port audio in SOUNDWIRE systems

Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.

I3C point to point

Systems and methods for multi-threshold sensing at an audio receiver, and systems and methods for calibrating an audio system to optimize for the specific configuration of the audio system are disclosed herein. In some implementations of a multi-threshold receiver, at least one additional voltage level is selected to trigger latching events within the receiver based on changes of the receiver input (which includes differential signals Vp and Vn) and in turn, to generate internal signals within the multi-threshold receiver, and then logic operations are performed on these internal signals to generate the output of the multi-threshold receiver.

Receiver and decoder for extreme low power, unterminated, multi-drop serdes

Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.

Latency optimized I3C virtual GPIO with configurable operating mode and device skip

Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

Slave-to-slave direct communication

System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.

High bandwidth soundwire master with multiple primary data lanes

Systems, methods, and apparatus are described that enable communication of in-band reset signals over an I3C serial bus. A method performed at a slave device includes driving a data line of the I3C serial bus from a high state to a low state before a first clock pulse is received from a clock line of the I3C serial bus after a start condition has been provided on the I3C serial bus, where driving the data line from the high state to the low state produces an initial pulse on the data line, transmitting one or more additional pulses on the data line before the first clock pulse is transmitted on the clock line, and driving the data line low until a rising edge of the first clock pulse is detected on the clock line after each of the plurality of additional pulses has been successfully transmitted on the data line.

Urgent in-band interrupts on an I3C bus

Systems, methods, and apparatus are described. An apparatus provides a clock signal, transmits an address on a second line of the serial bus followed by a read/write bit configured to initiate a read transaction, and delays a pulse in the clock signal after transmitting the read/write bit. The pulse may be delayed for a first duration configured to accommodate a latency associated with a first slave device that is a participant in the read transaction. The apparatus may receive an acknowledgement from the first slave device while the pulse is being transmitted and may receive a first data byte from the first slave device after receiving the acknowledgment. The apparatus may stall the clock signal for a second duration after receiving the first data byte from the first slave device, and receive a second data byte from the first slave device after the acknowledgment.

I3C read from long latency devices

Exemplary aspects of the present disclosure assist in phase alignment for systems having multiple audio sources. For example, in a system having plural microphones, phase alignment may also be assisted by sampling the microphones at the appropriate time relative to when the samples are placed on the audio bus. Further, phase shifts between audio samples are reduced or eliminated by keeping a sample delay constant for samples from the same microphone. Such manipulation of the audio samples reduces phase shifts which reduces the likelihood of an audio artifact capable of being detected by the human ear and thus improves consumer experience.

Phase alignment in an audio bus

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Yokneam, Israel

Lior Amarilio