Stmicroelectronics (rousset) Sas

St-ericsson Sa

Lionel Sinegre

William Orlando

Layachi Daineche

Stephan Courcambeck

Eric Sagnard

Eric Cerato

A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

Method for managing a return of a product for analysis and corresponding product

An interfacing circuit comprising a First In First Out (FIFO) memory for exchanging data between a 'data producer device' and a 'data consumer device'. The FIFO memory is controlled by first write control signals (WR, CLK_WR) and second read control signals (ENABLE, Clk_Rd). The interfacing circuit further includes: a redundancy filter () for receiving a sequence of N data (Y, Y, Y. . . Y) to be stored within said FIFO, and for generating a redundancy control word representative of the presence of consecutive identical data within said sequence; means () for controlling said first and said second control signals of said FIFO for the purpose of preventing the storage into said FIFO of multiple consecutive identical data and more important to make possible to accelerate the average speed of the data flux going to the &#x201c;data consumer device&#x201d; without need to accelerate the clocking of the memory feeding the said FIFO thanks to increase of efficiency of transfers due to redundancy filtering.

Interfacing circuit comprising FIFO storage in order to determine when to prevent multiple consecutive non-identical data based on difference threshold

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Nice, France

Lionel Sinegre