Intel Corporation

Lionel S Smith

Derek L Davis

Pranav H Mehta

Nicholas Ong

Robert Wickersheim

Steven D Gorman

A Ira Horden

A wireless authentication system to control an operating state of a node being a computer, door control mechanism or any muti-state product based on the proximity of an authorized user to the node. The wireless authentication system comprises a security device implemented within the computer and a user authentication token ('token') in possession of the authorized user. A Challenge/Response protocol is configured between the security device and the token. The first successful Challenge/Response message exchange between the security device and the token places the node in an operational state allowing the authorized user access to the contents and/or networked resources of the node. Later Challenge/Response message exchanges are set to occur periodically to check whether the authorized user possessing the token has left the node unattended thereby causing the node to be placed in a non-operational state.

Authentication system based on periodic challenge/response protocol

A method and system for reducing power consumption in a processor core. A state machine is used to coordinate a frequency from a clock signal generator with a voltage from a voltage regulator which is sufficient to allow operation of the processor at that frequency. Both the clock signal generator and the voltage regulator must be able to generate at least two frequencies or voltages, respectively. A level of processor need is tracked and the lowest frequency/voltage pair that will allow the processor core to satisfy the need is selected. The level of processor need is monitored either periodically or continually such that a new frequency/voltage pair can be dynamically selected as the application mix changes.

Method and apparatus providing multiple voltages and frequencies

A method and apparatus for configuring the address space of a computer is described. According to the present invention, a computer system has a full address space and includes at least one base unit, at least one expansion unit and a microprocessor core. The microprocessor core issues access addresses. The full address space includes a base address space and an expanded address space. The base address space is addressed by an M bit address and the expanded address space is addressed by an N bit address (N.gtoreq.M). Each base unit is mapped to an address within the base address space, and the base unit address is mirrored in the expanded address space. Each expansion unit is mapped to an address within the expanded address space. An address configuration circuit in the computer system includes an address space remapping circuit for selectively remapping or not remapping base units out of the base address space. The address configuration circuit also includes an expanded space enabling circuit for selectively enabling or disabling the expanded address space. Expansion units are accessible in the expanded address space depending upon whether the expanded address space has been enabled.

Address space manipulation in a processor

A system and method for preventing a copy of a document to the output from a printing node until the printing node authenticates the intended recipient. The system includes a sending node, a printing node and a communication link coupling these nodes together in a network fashion. The sending node has access to a public key of the printing node and uses this public key to encrypt a header and document before transmission to the printing node over the communication link. The priority node has access to its private key to decrypt the header to ascertain whether the document requires authentication by the intended recipient before being output.

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Queen Creek, AZ, United States of America

Lionel S Smith