Nxp B.v.

Ipdia

Lionel Guiraud

Herve Marie

Johan Hendrik Klootwijk

Freddy Roozeboom

David D R Chevrie

Francois Lecornec

In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

Source or emitter follower buffer circuit and method with mirrored current

Source or emitter follower buffer circuit and method

The invention relates to an electric device including an electric element, the electric element comprising a first electrode () having a first surface () and a pillar (), the pillar extending from the first surface in a first direction (), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section () perpendicular to the first direction and the pillar having a sidewall surface () enclosing the pillar and extending in the first direction, characterized in&#x2014;that, the pillar comprises any one of a score () and protrusion () extending along at least part of the length of the pillar for giving the pillar () improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.

Electronic device having electrode with high area density and improved mechanical stability

An electronic circuit for providing a logic gate function includes a differential signal input, a combining stage, a discriminating stage and a differential signal output. The discriminating stage includes four transistors each having first electrodes and second electrodes and a respective gate electrode. The first electrodes of the four transistors are connected to a common node. The combining stage is arranged to convert differential input signals into gate signals applied to the gate electrodes of some of the four transistors respectively.

Circuit for providing a logic gate function and a latch function

Growing community of inventors

Blainville sur Orne, France

Lionel Guiraud