Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Lionel Bening

Bryan D Hornung

Kenneth Chaney

Robert Pflederer

A method of providing hardware description language-embedded regular expression support for module iteration and interconnection. Regular expressions such as those used in the Perl programming language are used in a preprocessing process to generate instances and interconnections in a hardware description to automate the generation of repetitive code for a Hardware Description Language (HDL). This is accomplished by generating HDL code with embedded regular expressions, analyzing the code to identify the regular expressions and checking to see that the code complies with the HDL grammar rules. A data structure is generated for each module or submodule and these data structures are then elaborated to expand them into the instances and interconnections. A text generator traverses the elaborated data structures and generates HDL compliant text.

Hardware description language-embedded regular expression support for module iteration and interconnection

The inventive mechanism generates reproducible random initial states for use in simulation testing a design of a logic machine. The mechanism uses the hierarchical path names for the modules of the design and a random seed to generate reproducible random initialization states. Since the path names and the seed are known quantities, the random number can be reproduced. This allows the logic designs to be tested by different simulation methods and still have the same initialization states. Furthermore, if the simulation fails, design changes can be verified by using the same initialization states which caused the failure.

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Plano, TX, United States of America

Lionel Bening