International Business Machines Corporation

Linton B Ward, Jr

Benjiman L Goodman

Samuel I Ward

Joshua P Hernandez

Sunil Jeevananda Kamath

Bernhard K Schiefer

Sertac Cakici

A method of managing power in a computing system is provided. The method comprises: assessing incoming work; assessing service level agreements related to the incoming work; and coordinating with an operating system layer to control hardware of the computing system based on the service level agreements and a power consumption goal.

Coordinated approach between middleware application and sub-systems

A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.

Hardware process trace facility

A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.

System and method for power reduction through power aware latch weighting of complex sub-circuits

A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.

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Austin, TX, United States of America

Linton B Ward, Jr