Cvc Products, Inc.

Texas Instruments Corporation

Salutron, Inc.

Lino A Velo

Mehrdad M Moslehi

Ajit P Paranjpe

Randhir S Bubber

Thomas R Omstead

David R Campbell, Sr

Sanjay Gopinath

Habib N Najm

Boris Relja

David M Leet

Yong Jin Lee

John W Kuehne

Guihua Shang

Zeming Liu

Somnath Banerjee

Described herein are user-wearable devices, and methods for use therewith, for monitoring for one or more types of arrhythmias based on a photoplethysmography (PPG) signal obtained using an optical sensor of a user-wearable device. A PPG based statistical and/or machine learning model is used to analyze a PPG signal, obtained using the optical sensor, to monitor for one or more types of arrhythmias including atrial fibrillation (AF). In response to detecting an arrhythmia based on the PPG signal, an electrocardiogram (ECG) signal is obtained using an ECG sensor of the user-wearable device. An ECG based statistical and/or machine learning model is used to analyze the ECG signal obtained using the ECG sensor of the user-wearable device to confirm or reject the arrhythmia detected based on the PPG signal and/or to perform arrhythmia discrimination. Obtained PPG and/or ECG signal segments can be provided to the model(s) to update the model(s).

Arrhythmia monitoring using photoplethysmography

Technology is described for a wearable sensor system including an accelerometer and a PPG optical sensor having light processing elements including at least one photodetector in at least one linear configuration sharing an axis of orientation with the accelerometer. Heart rate measurements determined from reflected light detected by a photodetector of the light processing elements in a linear configuration are co-sampled with accelerometer measurements for one of its axes sharing its orientation with the linear configuration, thus providing per axis measurements which provide more precise data points for more easily compensating for motion artifacts in heart rate data. A wrist wearable biometric monitoring device is also described which embodies the wearable sensor system and performs active motion artifact compensation.

Sensor system for heart rate measurement per axis of shared orientation

A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and time. The barrier can comprises a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Method for fabricating a semiconductor chip interconnect

A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Microelectronic interconnect material with adhesion promotion layer and fabrication method

Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput. Alternatively, the adhesion promotion techniques can avoid the formation of an interface by graduated deposition of a first material and copper.

Method for forming a copper film on a substrate

A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and tin. The barrier can comprise a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization in one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Semiconductor chip interconnect barrier material and fabrication method

A method and apparatus are disclosed for depositing a tantalum-containing diffusion barrier, such as a TaN barrier layer, by dissolving a tantalum-bearing organometallic precursor, such as PEMAT or PDEAT, in an inert, low viscosity, high molecular weight, low volatility solvent, such as octane, heptane, decane or toluene. The precursor-solvent solution is vaporized and flowed over a substrate to deposit the barrier. The precursor solution has a viscosity substantially similar to that of the solvent by maintaining the ratio of precursor to solvent at a generally low value, such as approximately 10% precursor. The boiling point of the solvent is substantially similar to the boiling point of the precursor, such as within 50% of the precursor boiling point at one atmosphere, to enhance repeatability of barrier film quality. Resistivity of the barrier film is reduced by flowing a reactive gas with the precursor flow, the reactive gas reducing the carbon content of the barrier film, or by co-deposition of a resistivity-lowering metallic dopant with the precursor solution. Alternatively, resistivity is reduced by controlling the nitrogen content of the film by a post-deposition plasma treatment of the barrier with a reducing gas.

Method and apparatus for depositing tantalum-based thin films with organmetallic precursor

A method for calibrating at least one temperature sensor. A wafer (30) having calibration structures of a material having a melting point in the range of 150.degree. to 1150.degree. C. is provided. The temperature sensor is operable to detect a temperature dependent characteristic of the wafer and output a signal corresponding to the temperature depending characteristic. The power input is selectively varied and the wafer temperature is ramped for a calibration run. A wafer characteristic, such as wafer reflectance, radiance, or emissivity, is monitored. A first step change in the wafer characteristic corresponding to a wafer temperature equal to the melting point of the calibration structures is detected and a set of calibration parameters for each temperature sensor being calibrated is calculated.

Wireless temperature calibration device and method

In a RTP reactor where wafer temperature is measured by a pyrometer assembly (32), a pyrometer assembly (50) is further provided to measure the temperature of the quartz window (30) that is situated between the wafer pyrometer assembly (32) and the wafer (16) that is being processed. During the calibration procedure (100, 120) where a thermocouple wafer is used, the measurements from the wafer pyrometer assembly (32) and the window pyrometer assembly (50) are calibrated, and pyrometer measurements and thermocouple measurements are collected and compiled into calibration tables. During actual RTP reactor operation, the data from the calibration tables and current wafer and window pyrometer measurements are used to compute corrected wafer temperature(s). The corrected wafer temperature(s) is/are then used to control the intensities of the heating lamps according to the wafer processing heating schedule.

Apparatus and method for determining wafer temperature using pyrometry

Several process flows are proposed for achieving suitable wafer backside structures for integrated RTP-based device processing. The wafer backside conditions proposed here can be adapted for integrated fabrication process flows based on multiple integrated single-wafer and rapid thermal processing (RTP) cycles. These backside conditions ensure repeatable RTP uniformity and accurate pyrometry calibrations and measurements. The use of a highly doped layer near the wafer backside ensures negligible infrared transmission and repeatable RTP-based process uniformity, both for the high-temperature and the lower temperature RTP-based processes such as low-pressure chemical-vapor deposition of silicon. Two backside layers are used (oxide and nitride) to prevent dopant outdiffusion and backside oxide growth due to thermal oxidation. Moreover, the backside silicon nitride layer preserves uniform backside emissivity throughout the entire flow. This is due to the oxidation resistance and also etch resistance of silicon nitride. The backside structures disclosed prevent emissivity variations/drift during RTP and other device fabrication steps throughout an integrated flow.

Conditioning of semiconductor wafers for uniform and repeatable rapid

A device and method for calibrating at least one temperature sensor is disclosed herein. A wafer (30) is provided having a first plurality of calibration islands (36) of a material having a melting point in the range 150.degree.-1150.degree. C. The effective reflectivity of the wafer is measured in operation using the temperature sensor or via a separate light source. A first step change in an output signal of the temperature sensor corresponding to a wafer temperature equal to the melting point of the first calibration islands is detected. Finally, the temperature sensor calibration parameters are calculated.

Growing community of inventors

Dallas, TX, United States of America

Lino A Velo