Xilinx, Inc.

Other

Beijing Deephi Intelligent Technology Co., Ltd.

Lingzhi Sui

Yi Shan

Qian Yu

Shaoxia Fang

Junbin Wang

Yu Zhang

Xin Peng Liu

Xiang Feng

Hong Luo

Xiaoming Sun

Song Yao

Yushun Wang

Chong Sun

Enshan Yang

Xianpei Zheng

Zhongmin Chen

Pengbo Zheng

A system includes a high bandwidth memory (HBM) and a convolutional neural network (CNN) engine. The HBM includes a virtual bank portion and a system memory portion. The virtual bank portion is configured to store a feature map data and the system memory portion is configured to support data exchanges with a host. The CNN engine includes a convolutional unit configured to execute convolutional layer instructions, a depthwise convolutional unit configured to execute depthwise layer instructions, and a first on-chip buffer. The first on-chip buffer is configured to receive and store the feature map data from the virtual bank portion or receive and store data results from the convolutional unit. The first on-chip buffer is further configured to send the feature map data or the data results from the convolutional unit to the depthwise convolutional unit for processing.

Neural network architecture with high bandwidth memory (HBM)

The present invention discloses a method to optimize a neural network computational graph. The computational graph is used for performing neural network calculation by a computational platform. The computational platform reads data needed by the calculation from off-chip memory. The method comprises: layers which can be fused are selected at least based on an optimization rule to reduce frequency of data exchange between the computational platform and the off-chip memory, carrying out fusion for at least two adjacent layers in the computational graph according to the selected layer objects. Here, the at least two adjacent layers are at least one of the following: horizontally adjacent layers having the same input of feature maps; and longitudinally adjacent layers in which the calculation results of a feature map of a previous layer are at least part of input for a next layer. The method to optimize a computational graph of the present invention can be automatically carried out based on rules or through isomorphic subgraph matching. Thus, an optimal reconstruction mode for executing the computational graph is found out, execution efficiency of the neural network computational platform is improved.

Methods of optimization of computational graphs of neural networks

A high parallelism computing system and instruction scheduling method thereof are disclosed. The computing system comprises: an instruction reading and distribution module for reading a plurality of types of instructions in a specific order, and distributing the acquired instructions to corresponding function modules according to the types; an internal buffer for buffering data and instructions for performing computation; a plurality of function modules each of which sequentially executes instructions of the present type distributed by the instruction reading and distribution module and reads the data from the internal buffer; and wherein the specific order is obtained by topologically sorting the instructions according to a directed acyclic graph consisting of the types and dependency relationships. By reading the instructions based on the topological sorting the directed acyclic graph constructed according to the types and dependency relationships, the deadlock caused by the instruction dependencies can be avoided by a relatively simple operation.

High parallelism computing system and instruction scheduling method thereof

The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer module, a convolution operation unit and a hybrid computation unit. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.

Device for implementing artificial neural network with separate computation units

The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer pool, a data reading scheduling unit and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.

Device for implementing artificial neural network with flexible buffer pool structure

The disclosure provides a compilation method and system for heterogeneous computing platform, and a runtime method and system for supporting program execution on the heterogeneous computing platform. Inputting a trained neural network model to a Neural Network (NN) optimizing compiler to generate an NN assembly file corresponding to the neural network; inputting the NN assembly file to an NN assembler to generate an NN binary file corresponding to the neural network; compilation and assembling a neural network application developed by users in a high-level language using a host compiler toolchain to generate a corresponding host assembly file and a host binary file in sequence; and linking the NN binary file and the host binary file using a host linker to generate a single hybrid linking executable file. The technical solution of the present disclosure has the advantages such as good computing performance, strong scalability, strong compatibility and high flexibility.

Programming model of neural network-oriented heterogeneous computing platform

The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, a first instruction unit, a second instruction unit, an instruction distributing unit, a data transferring controller, a buffer module and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.

Growing community of inventors

Beijing, China

Lingzhi Sui