Intel Corporation

Lingjing Zeng

Russell Jerome Fenger

Deepak Samuel Kirubakaran

Marc D Torrant

Ashraf H Wadaa

Noor Mubeen

Andrey Gabdulin

Ryan Thompson

Georgina Saborio Dobles

Yanbai Wang

A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vfor energy-efficiency. Such Vvalues may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest V. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest V. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

Energy-efficient core voltage selection apparatus and method

Device and method for reporting power-on self-test (POST) codes of a computing device via a standard external memory card interface. A BIOS of the personal computing device is programmed to configure, during a power-on sequence, multiple signal connections of the standard external memory card interface for conveyance of general purpose input and output signals. When a complementary memory signal conversion device is detected in the memory card interface during the power-on sequence, the BIOS may initiate transmission of a serial data signal containing POST codes related to any detected startup errors.

Post code reporting via secure digital memory interface

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Shanghai, China

Lingjing Zeng