Broadcom Corporation

Zarlink Semiconductor Limited

Inphi Corporation

Conexant Systems, Inc.

Clariphy Communications, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Marvell Asia Pte., Ltd.

Avago Technologies International Sales Pte. Limited

Promise Technology, Inc.

Istor Networks, Inc.

Linghsiao Wang

Peiqing Wang

Marcel Louis Lugthart

Jeffrey Zachan

Rong-Feng Chang

Mehmet Vakif Tazebay

Craig Barrack

Scott R Powell

James Ching-Shau Yik

Norman L Swenson

Paul Voois

Kishore Kota

Li Xu

Arash Farhoodfar

Neel H Patel

Xiaotong Lin

Afshin Mellati

Eric Xin Lin

Kuoruey Han

James Yik

Liang Fan

Quanli Lu

Cindra Abidin

Espen Olsen

Brian Yang

Eric (Changhwa) Lin

Kuoruey (Ray) Han

A time-interleaved digital-to-analog converter for an optical transmitter includes a DAC core having a plurality of slices and current sources for converting complementary data signals to analog signals at output nodes of the DAC core, a down switch circuitry configured to connect, for each slice of the DAC core, a current from one of the current sources to a first data input path or a second data input path respectively corresponding to first complementary data signals and second complementary data signals supplied to the slice of the DAC core, an up switch circuitry configured to connect the current to the output nodes, and a data switch circuitry configured to, for each slice of the DAC core, selectively connect the current received via the down switch circuitry and either the first data input path or the second data input path.

Low power time-interleaving DAC with pseudo interleaved architecture

Systems and methods for implementing an Energy-Efficient Ethernet (EEE) communication are provided. In some aspects, a method includes identifying an EEE signal configured to be communicated via a first set of wires. The method also includes processing the EEE signal such that the processed EEE signal is configured to be communicated via a second set of wires. The second set of wires including fewer wires than the first set of wires. The method also includes communicating the processed EEE signal via the second set of wires.

Systems and methods for implementing energy-efficient ethernet communications

Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.

Deskew in a high speed link

High speed transceiver

Channel negotiation for a high speed link

Systems and methods for implementing bi-directional synchronization propagation between first and second communication devices are provided. The devices are arranged in a loop-timing configuration. A method includes detecting, by the second communication device, a switching signal comprising an indication to switch a timing role of the second communication device and engaging, by the second communication device, in a synchronization handshake with the first communication device over a communication link based on the detection of the switching signal. Engaging in the synchronization handshake includes determining whether the first communication device is configured to support bi-directional synchronization propagation. The method includes switching the timing role of the second communication device based on the synchronization handshake.

Systems and methods for implementing bi-directional synchronization propagation

Timing recovery in a high speed link

Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Method and system for unconstrained frequency domain adaptive filtering

A system for reduced pair Ethernet transmission. The system includes an interleaver that is operable to receive sets of four code symbols from a physical channel sub-layer (PCS) encoder, wherein each code symbol of each set of four code symbols is associated with one of four channels, and interleave the sets of four code symbols to generate a plurality of interleaved code symbols. The system further includes a serializer that is operable to serialize the plurality of interleaved code symbols to generate a plurality of interleaved and serialized code symbols. The system further includes a transmitter that is operable to transmit the plurality of interleaved and serialized code symbols over an Ethernet medium comprising a single twisted pair of wires.

Reduced pair Ethernet transmission system

A system and method for loop timing update of energy efficient physical layer devices using subset communication techniques. During a quiet period during which a subset of communication channels are transitioned from an active mode to a low-power mode, circuitry in the active channel can be designed to track, on behalf of the inactive channels, the phase drift due to the frequency offset. This tracking of the frequency estimation error would reduce the time required to perform a timing update for the communication channels when transitioning back to the active mode.

System and method for loop timing update of energy efficient physical layer devices using subset communication techniques

Embodiments of a dual-master mode Ethernet node are provided herein. The dual-master mode Ethernet node includes a first multiplexer configured to select between a local oscillator signal and a primary reference source (PRS) signal to provide a reference clock signal, a digital phase-locked loop (DPLL) configured to generate a master clock signal based on the reference clock signal, a phase rotator configured to rotate a phase of the master clock signal based on a frequency error between the master clock signal and an extracted clock signal to generate a slave clock signal, and a second multiplexer configured to select between the master clock signal and the slave clock signal to provide a transmit clock signal. The dual-master mode Ethernet node can dynamically generate the transmit clock based on either the extracted clock or the PRS without re-performing the auto-negotiation process.

Systems and methods for providing a dual-master mode in a synchronous ethernet environment

Growing community of inventors

Irvine, CA, United States of America

Linghsiao Wang